Universidad Mayor Nacional San Marcos

Facultad de Ingenieria electrica y electronica

Tarea Nro 1 VHDL

Alumno: Huahuala Cuyubamba Rolando
Código: 16190127
Profesor: Ing. Ruben Alarcon Matutti
Solucion:
1)

a)

library ieee;

use ieee.std_logic_1164.ALL;

entity problema1 IS

PORT(

A,B,C,D : IN STD_LOGIC;

F : OUTSTD_LOGIC);

end problema1 ;

architeture solucion of problema1 IS

begin

F <= (A AND NOT(C)) OR (B AND NOT(C)) OR (NOT(C) AND NOT(D)) OR (A AND B) OR (A AND
NOT(D)) ;

end solucion;
b)

library ieee;

use ieee.std_logic_1164.ALL;

entity problema1 IS

port(

A,B,C,D : IN STD_LOGIC;

F : OUTSTD_LOGIC);

end problema1 ;

architeture solucion of problema1 IS

begin

F <=( A OR NOT(C)) AND ( A OR B OR NOT(D)) AND (B OR NOT(C) OR NOT(D)) ;

end solucion;

2)

a)

library ieee;

use ieee.std_logic_1164.ALL;

entity problema1 IS

PORT(

A,B,C,D : IN STD_LOGIC;

F : OUTSTD_LOGIC);

end problema1 ;

architeture solucion of problema1 IS

begin

F <= ((x I AND x3) OR (NOT xl AND NOT x3)) OR {R2 AND x4) OR (NOT x2 AND NOT x4));

end solucion;
b)

library ieee;

use ieee.std_logic_1164.ALL;

entity problema1 IS

port(

A,B,C,D : IN STD_LOGIC;

F : OUTSTD_LOGIC);

end problema1 ;

architeture solucion of problema1 IS

begin

F <= (x 1 AND x2 AND NOT x3 AND NOT x4) OR (NOT x 1 AND N-OT x2 AND x3 AND x4) (xl AND NOT
x2 AND NOT AND x4) OH (NOT x 1 AND x2 AND x3 AND NOT x4);

END solucion;

3) Escriba el código de VHDL para implementar la función 𝑓(𝑥1 + 𝑥2 + 𝑥3 + 𝑥4 ) =

∑ 𝑚(0,1,2,4,5,7,8,9,11,12,14,15)

library ieee;
use ieee.std_logic_1164.all;
entity obligatorio1 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio1;

architecture FuncLogic of obligatorio1 is

begin
f <= ((not x1 and not x3) or (not x2 and not x3) or (not x1 and not x2 and not x4) or (x2 and not x4)
or (x1 and x3 and x4) or (x1 and x2 and not x4));
end FuncLogic;
 4) Escriba el código de VHDL para implementar la función:
𝑓(𝑥1 , … . . , 𝑥4 ) = ∑ 𝑚(1, 4, 7, 14, 15) + 𝐷(0, 5, 9)

library ieee;
use ieee.std_logic_1164.all;
entity obligatorio2 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio2;

architecture FuncLogic of obligatorio2 is

begin
f <= ((not x1 and not x3) or (not x1 and x2 and x4) or (x1 and x2 and x3));
end FuncLogic;

5) Escriba el código de VHDL para implementar la función:

f(x1 , … . . , x4 ) = ∏ M(6, 8, 9, 12, 13)

library ieee;
use ieee.std_logic_1164.all;
entity obligatorio3 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio3;

architecture FuncLogic of obligatorio3 is

begin
f <= (not x1 or x3) and (x1 or not x2 or not x3 or x4);
end FuncLogic;
 6) Escriba el código de VHDL para implementar la función:
f(x1 , … . . , x4 ) = ∏ M(3, 11, 14) + D(0, 2, 10, 12)

library ieee;
use ieee.std_logic_1164.all;
entity obligatorio4 is
port (x1 : in std_logic;
x2 : in std_logic;
x3 : in std_logic;
x4 : in std_logic;
f : out std_logic);
end obligatorio4;

architecture FuncLogic of obligatorio4 is

begin
f <= (x2 or not x3) and (not x1 or not x3 or x4);
end FuncLogic;