UNIVERSIDAD NACIONAL MAYOR

DE SAN MARCOS
Universidad del Perú, DECANA DE AMERICA

FACULTAD DE INGENIERIA ELECTRONICA Y

ELECTRICA
 TEMA: Tarea VHDL
 CURSO: Circuitos Digitales
 PROFESOR: Ing. ALARCÓN MATUTTI RUBÉN
 ALUMNO:
 VILLAFUERTE HUAYLINOS, JHULIAN 15190138

2019 – 2
PROBLEMA 1

Codigo VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_ARITH.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY problema1 is
port ( A: in std_logic;
B: in std_logic;
S: in bit_vector (3 downto 0);
F: out std_logic);
end problema1;
architecture solucion of problema1 is
begin
with S select
F<= (NOT A) when "0000",
(Not (A and B)) when "0001",
((Not A) or B) when "0010",
'1' when "0011",
(A xnor B) when "0100",
(Not B) when "0101",
(A xor B) when "0110",
(A or Not B) when "0111",
(A and B) or A when "1000",
A xor B when "1001",
B when "1010",
A or B when "1011",
'0' when "1100",
A and (B xor A) when "1101",
A and B when "1110",
A when "1111";
end solucion;
 Waveform Editor

2.47 a) Escriba el código VHDL para describir las funciones siguientes:

f 1=x 1 . x́ 3+ x 2 . x´3 + x́ 3 . x´4 + x 1 . x 2+ x 1 . x´4

f 2=( x 1+ x́3 ) . ( x 1+ x 2 + x́ 4 ) . ( x 2+ x´3 + x́ 4 )

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity pregunta2 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

f1,f2:OUT STD_LOGIC);

end pregunta2;

architecture dataflow of pregunta2 is

signal s1,s2,s3,s4,s5,s6,s7,s8: STD_LOGIC;

constant gate_delay: Time:=5 ns;

begin

L1:s1<=x1 and (not x3) after gate_delay;

L2:s2<=x1 and x2 after gate_delay;

L3:s3<=x2 and (not x3) after gate_delay;

L4:s4<=(not x3) and (not x4)after gate_delay;

L5:s5<=x1 and (not x4)after gate_delay;

L6:s6<=s1 or s2 after gate_delay;

L7:s7<=s3 or s4 after gate_delay;

L8:s8<=s7 or s5 after gate_delay;

L9:f1<=s8 or s6 after gate_delay;

f2<=(x1 or(not x3))and(x1 or x2 or(not x4))and(x2 or(not x3) or(not x4));

end dataflow;
 b) Use simulación funcional para probar que f 1=f 2

2.48 Considere las instrucciones siguientes de asignación en VHDL

F1<=((x1 and x3)or(not x1 and not x3))or((x2 and x4)or(not x2 and not x4));

F2<=(x1 and x2 and not x3 and not x4)or(not x1 and not x2 and x3 and x4)

or(x1 and not x2 and not x3 and x4)or(not x1 and x2 and x3 and not x4);

a) Escriba el código VHDL para describir las funciones:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity pregunta248 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1,F2:OUT STD_LOGIC);

end pregunta248;

architecture solucion of pregunta248 is

begin

F1<=((x1 and x3)or(not x1 and not x3))or((x2 and x4)or(not x2 and not x4));

F2<=(x1 and x2 and not x3 and not x4)or(not x1 and not x2 and x3 and x4)

or(x1 and not x2 and not x3 and x4)or(not x1 and x2 and x3 and not x4);

end solucion;b) Use simulación funcional para comprobar que f 1=f´2

4.38. Escriba el codigo VHDL para implementar la siguiente función
f ( x 1 … x 4 )=∑ m( 0,1,2,4,5,7,8,9,11,12,14,15)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity problema438 is

port( x : in std_logic_vector(3 downto 0);

F : out std_logic_vector (0 downto 0));

end problema438 ;

architecture solucion of problema438 is

begin
with x select F<="1" when "0000",

"1" when "0001",

"1" when "0010",

"1" when "0100",

"1" when "0101",

"1" when "0111",

"1" when "1000",

"1" when "1001",

"1" when "1011",

"1" when "1110",

"1" when "1111",

"0" when others;

end solucion;
4.39. Escriba el codigo VHDL para implementar la siguiente función
f ( x 1 … x 4 )=∑ m ( 1,4,7,14,15 ) + D(0,5,9)

f 1=. x́1 . x´3 + x 2 . x 3 . x 4 + x 1 . x 2 . x 3

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity problema439 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1:OUT STD_LOGIC);

end problema439;

architecture solucion of problema439 is

beginF1<=((not x1) and (not x3))or( x2 and x3 and x4)or(x1 and x2 and x3)

end solucion;
4.40 Escriba el codigo VHDL para implementar la siguiente función

f ( x 1 … x 4 )=∏ M (6,8,9,12,13)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;
entity problema440 is

port( x : in std_logic_vector(3 downto 0);

F : out std_logic_vector (0 downto 0));

end problema440 ;

architecture solucion of problema440 is

begin

with x select F<="1" when "0000",

"1" when "0001",

"1" when "0010",

"1" when "0011",

"1" when "0100",

"1" when "0101",

"1" when "0111",

"1" when "1010",

"1" when "1011",

"1" when "1110",

"1" when "1111",

"0" when others;

end solucion;
4.41. Escriba el codigo VHDL para implementar la siguiente función

f ( x 1 … x 4 )=∏ M (3,11,14)+ D( 0,2,10,12)

f 1=( x 2+ x́3 ) ( x´1 + x́ 2 + x 4 ¿ )

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity problema441 is

port( x1:in STD_LOGIC;

x2:in STD_LOGIC;

x3:in STD_LOGIC;

x4:in STD_LOGIC;

F1:OUT STD_LOGIC);

end problema441;

architecture solucion of problema441 is

begin
F1<=(x2 and (not x3)) or ( (not x1) and (not x2) and x4);

end solucion;