Experiment-3

Aim: Design,Synthesis and Simulate multiplexer circuit using Xilinx tool.

Activity1 Write a VHDL code for 4*1 bit level mux using 2*1 mux in structure modeling.

Truth Table

Boolean expression:- s=(a.s’)+(b.s)

VHDL Code(Implementation) for 2*1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux1 is
Port ( a,b,s : in STD_LOGIC;
y : out STD_LOGIC);
end mux1;
architecture Behavioral of mux1 is
begin
y<=(a and (not s)) or (b and s);
end Behavioral;
Circuit diagram of 2x1 mux
VHDL Code for 4*1 Mux
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4 is
Port ( a,b,c,d,s1,s0 : in STD_LOGIC;
y1 : out STD_LOGIC);
end mux4;
architecture Behavioral of mux4 is
component mux1 is
Port ( a,b,s : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal t1,t2: STD_LOGIC;
begin
m1:mux1 port map(a,b,s1,t1);
m2:mux1 port map(c,d,s1,t2);
m3:mux1 port map (t1,t2,s0,y1);
end Behavioral;

Boolean expression:- Y = S1’.S0’. a + S1’.S0. b + S1.S0’ .c + S1.S0. d

Circuit diagram:-

Schematic Diagram
VHDL CODE(Testbench)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux41 IS
END mux41;
ARCHITECTURE behavior OF mux41 IS
COMPONENT mux4
PORT(
a : IN std_logic;b : IN std_logic;
c : IN std_logic; d : IN std_logic;
s1 : IN std_logic;s0 : IN std_logic;
y1 : OUT std_logic );
END COMPONENT;
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';
signal s1 : std_logic := '0';
signal s0 : std_logic := '0';
signal y1 : std_logic;
BEGIN
uut: mux4 PORT MAP (
a => a, b => b,
c => c, d => d,
s1 => s1, s0 => s0,
y1 => y1 );
stim_proc: process
begin
a<='0';b<='0';c<='1';d<='1';s1<='0';s0<='0';wait for 100 ns;
a<='1';b<='0';c<='1';d<='1';s1<='0';s0<='1';wait for 100 ns;
a<='0';b<='1';c<='1';d<='1';s1<='1';s0<='0'; wait for 100 ns;
a<='1';b<='1';c<='1';d<='1';s1<='1';s0<='1';wait for 100 ns;
wait;
end process;
END;

Waveform

Activity 2 Write a VHDL Code for 4*1 MUX Word level (n-bit) using 2*1 word level MUX.
Word level Code for 2*1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1wlevel is
generic(n:natural:=4);
Port ( a,b: in STD_LOGIC_vector(n-1 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_vector(n-1 downto 0));
end mux2to1wlevel;
architecture Behavioral of mux2to1wlevel is
component mux1 is
Port ( a,b,s : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin
loop1:for i in 0 to n-1 generate
mux1:mux1 port map(a(i),b(i),s,y(i));
end generate;
end Behavioral;

VHDL CODE(IMPLEMENTATION) for 4*1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1wlevel is
generic (n:natural:=8);
 Port ( a,b,c,d : in STD_LOGIC_vector(n-1 downto 0);
s : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC_vector(n-1 downto 0));
end mux4to1wlevel;
architecture Behavioral of mux4to1wlevel is
component mux2to1wlevel is
generic(n:natural:=8);
Port ( a,b: in STD_LOGIC_vector(n-1 downto 0);
s : in STD_LOGIC;
y : out STD_LOGIC_vector(n-1 downto 0));
end component;
signal p1,p2:std_logic_vector(n-1 downto 0);
begin
m1:mux2to1wlevel generic map(n) port map(a,b,s(1),p1);
m2:mux2to1wlevel generic map(n) port map(c,d,s(1),p2);
m3:mux2to1wlevel generic map(n) port map(p1,p2,s(0),y);
end Behavioral;

circuit Diagram of 4x1 mux(word level)

Schematic Diagram
VHDL CODE(Test bench)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux4to1wleveltest IS
END mux4to1wleveltest;
ARCHITECTURE behavior OF mux4to1wleveltest IS
COMPONENT mux4to1wlevel
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
c : IN std_logic_vector(7 downto 0);
d : IN std_logic_vector(7 downto 0);
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic_vector(7 downto 0) );
END COMPONENT;
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal b : std_logic_vector(7 downto 0) := (others => '0');
signal c : std_logic_vector(7 downto 0) := (others => '0');
signal d : std_logic_vector(7 downto 0) := (others => '0');
signal s : std_logic_vector(1 downto 0) := (others => '0');
signal y : std_logic_vector(7 downto 0);
BEGIN
uut: mux4to1wlevel PORT MAP (
a => a, b => b,
c => c,d => d,
s => s,y => y);
stim_proc: process
begin
 a<="10000000";b<="00000001";c<="10000100";d<="01000001";s<="00";
wait for 100 ns;
a<="10000000";b<="00000101";c<="10000100";d<="01000001";s<="01";
wait for 100 ns;
a<="10000000";b<="00010001";c<="10010100";d<="01000001";s<="10";
wait for 100 ns;
a<="10000001";b<="00000001";c<="10000101";d<="01000001";s<="11";
wait for 100 ns;
wait;
end process;
END;

Wave form:-

Synthesis Report
2x1 mux 4x1 mux
Number of Slices: 2 out of 768 0% Number of Slices: 2 out of 768 0%
Number of 4 input LUTs: 4 out of 1536 0% Number of 4 input LUTs: 4 out of 1536 0%
Number of bonded IOBs: 13 out of 97 13% Number of bonded IOBs: 13 out of 97 13%
Delay: 7.504ns (Levels of Logic = 3)

Conclusion:-in 2x1 mux Number of Slices: 1 out of 768 0% Delay: 7.340ns (Levels of
Logic = 3)
And in 4x1 word level Number of Slices 1 out of7680% and delay is7.540ns