N-Bit Shift Register PDF

ELE432
ADVANCED DIGITAL DESIGN

HACETTEPE UNIVERSITY
Designing with VHDL
Organization of the Week
• Quartus II and simple I/O
• Combinational Design with VHDL
• Sequential Design with VHDL
DE1-SOC
DE1-SOC
• Altera Cyclone® V SE 5CSEMA5F31C6Ndevice
• Altera Serial Configuration device –EPCQ256
• USB Blaster II(on board) for programming; JTAG Mode
• 64MBSDRAM(16-bit data bus)
• 4 Push-buttons
• 10Slide switches
• 10Red user LEDs
• Six 7-segment displays
• Four 50MHz clock sourcesfrom clock generator
• 24-bitCD-quality audio CODEC with line-in, line-out, and microphone-in jacks
• VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
• TV Decoder (NTSC/PAL/SECAM) and TV-in connector
• PS/2 mouse/keyboard connector
• IR receiverand IR emitter
• Two40-pin Expansion Header with diode protection
• A/D Converter, 4-pin SPI interface with FPGA
Quartus II Standard Compilation Design Flow
Some types that
we need to
know:
*.sdc – timing
*.qsf – signal
*.sof – outputfile
Simulation
*.qsf
#============================================================
#Y
#============================================================
set_location_assignment PIN_V16 -to Y[0]
set_location_assignment PIN_W16 -to Y[1]
set_location_assignment PIN_Y19 -to Y[6]
set_location_assignment PIN_Y21 -to Y[9]
Pin
Planner
Simple Inputs and Outputs
Switch inputs
7 Segment LED’s
J-TAG Chain on board
High-Speed USB
Peripheral Controller
Simple Signal Assignments
VHDL has built-in support for the following operators
– and logical AND
– or logical OR
– not logical NOT
– nand, nor, xor, xnor
• VHDL does not assume any precedence of logic operators.
Use parentheses in expressions to determine precedence
– Exception to this is NOT logical operator
• In VHDL, a logic expression is called a simple assignment
statement. There are other types that will be introduced that
are useful for more complex circuits.
Signal Usage
• The assignment of a waveform value to a signal is referred to as

signal assignment.
• <= The only assignment operator which can be used to assign
waveforms to signals.
Signal Assignments
VHDL provides several types of statements that can be used to

assign logic values to signals
– Simple assignment statements
Used previously, for logic or arithmetic expressions
– Selected signal assignments
– Conditional signal assignments
– Generate statements
– If-then-else statements
– Case statements
Signal Usage
library ieee;
signal Q: std_logic_vector(0 to 7);
use ieee.std_logic_1164.all;
begin
entity shiftcomp is port(Clk, Rst, Load: in std_logic;
signal X1,X2.X3,DN: std_logic;
Init: in std_logic_vector(0 to 7);
m: process (Rst, Clk)
Test: in std_logic_vector(0 to 7);
begin
Limit: out std_logic);
if Rst = `1' then
end shiftcomp;
Q1 <= '0';
architecture structure of shiftcomp is
elsif Clk = `1' and Clk'event then
component compare
Q1 <= Grant;
port(A, B: in std_logic_vector(0 to 7); EQ: out bit);
end if;
end component;
end process;
component shift
DN <= X1 or X3 and X2;
port(Clk, Rst, Load: in std_logic;
COMP1: compare port map (Q, Test, Limit);
Data: in std_logic_vector(0 to 7);
SHIFT1: shift port map (Clk, Rst, Load, Init, Q);
Q: out std_logic_vector(0 to 7));
end structure;
end component;
Priority encoder
architecture behavioral of priority is
signal K,L,M:bit;
begin
Y(9 downto 2) <= (others => '0');
K <= not D(0) and D(1);
L <= not D(0) and not D(1) and D(2);
M <= (not D(0) and not D(1) and not D(2) and D(3));
Y(0) <= K or M;
Y(1) <= L or M;
end behavioral ;
Selected signal assignment
A selected signal assignment allows a signal to be assigned

one of several values, based on a selection criterion
– Keyword WITH specifies that s is used for the selection criterion
– Two WHEN clauses state that f=w0 when s=0 and f=w1 otherwise
– The keyword OTHERS must be used
architecture behavior of mux2to1 is
begin
with s select
f <= w0 when '0',
w1 when others;
end behavior;
MUX 4-1 example
library ieee;
entity mux4to1 is
port ( w : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
f : out std_logic);
end mux4to1;
begin
with s select
f <= w(0) when "00",
w(1) when "01",
w(2) when "10",
w(3) when others;
end behavior;
Decoder
entity dec2to4 is
port ( w : in std_logic_vector(1 downto 0);
en : in std_logic;
y : out std_logic_vector(0 to 3));
end dec2to4;
architecture behavior of dec2to4 is
signal enw : std_logic_vector(2 downto 0);
begin
enw <= en & w; -- ‘&’ is the vhdl concatenate operator
with enw select
y <= "1000" when "100",
"0100" when "101",
"0010" when "110",
"0001" when "111",
"0000" when others;
end behavior;
Conditional Signal Assignments:
Conditional Signal Assignments:
C <= a xor b;
-- or
C <='0' when a='0' and b='0' else
'1' when a='1' and b='1' else
'0';
Mux 2-1
entity mux2to1 is
port (w0, w1, s : in std_logic;
f : out std_logic);
end mux2to1;
begin
f <= w0 when s = '0' else w1;
end behavior;
Priority Encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Priority_Encoder_VHDL is
port ( Sel : in std_logic_vector(3 downto 0);
encoded_data : out std_logic_vector(1 downto
0);
D : out std_logic);
end entity Priority_Encoder_VHDL;
architecture Behavioral of Priority_Encoder_VHDL is

begin
encoded_data <=
"11" when Sel(3)='1' else
"00";
D <= '0' when Sel="0000" else '1';
end architecture Behavioral;
1bit full adder and package decleration
library ieee ; library ieee;

use ieee.std_logic_1164.all ; use ieee.std_logic_1164.all;
entity fulladd is package fulladd_package is
port ( cin, x, y : in std_logic; component fulladd
s, cout : out std_logic); port ( cin, x, y : in std_logic;
end fulladd ; s, cout : out std_logic);
architecture logicfunc of fulladd is end component;
begin end fulladd_package;
s <= x xor y xor cin;
cout <= (x and y) or (cin and x) or (cin and y);
end logicfunc;
4 bit adder
library ieee;
use work.fulladd_package.all;
entity adder4 is
port ( cin : in std_logic;
x, y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end adder4;
architecture structure of adder4 is
signal c : std_logic_vector(1 to 3);
begin
stage0: fulladd port map ( cin, x(0), y(0), s(0), c(1) );
stage1: fulladd port map ( c(1), x(1), y(1), s(1), c(2) );
stage3: fulladd port map ( c(3), x(3), y(3), s(3), cout );
end structure;
Structural Descriptions
The previous VHDL code examples are termed behavioral VHDL because they
describe the behavior of a circuit without describing exactly how it is
implemented in hardware.
• Another VHDL coding style is structural.
– For structural VHDL, the user typically describes the structure of a design by
interconnecting several simpler designs from a library
• The library components may be user-defined or provided by the CAD tool
vendor.
Component Instantiation
entity design is
port (a, ck, mr, din: in bit;
rdy, ctrlsig: out bit);
end design;
architecture structure of design is MR
RDY
component and2
port(x,y: in bit :=‘0’; z: out bit); Q
S1
A
end component; D
QBAR
component nor2
port(a,b: in bit; z: out bit); ctrlsig S2
end component;
component dff
CK
port(d, clock: in bit; qbar: out bit); CTRLS
open
end component;
signal s1,s2: bit;
begin
d1:dff port map(a,ck,s1,s2);
a1:and2 port map(s2,open,ctrlsig);
n1:nor2 port map(a=>s1, z=>rdy, b=>mr);
end structure
Example for structural representation
library ieee ;
use ieee.std_logic_1164.all ;
entity fulladd is
port ( cin, x, y: in std_logic; s,cout: out std_logic);
end fulladd ;
architecture logicfunc of fulladd is
begin
s <= x xor y xor cin;
cout <= (x and y) or (cin and x) or (cin and y);
end logicfunc;
Use of package fulladd_package
library ieee;
package fulladd_package is
component fulladd
port ( cin, x, y : in std_logic;
s, cout : out std_logic);
end component;
end fulladd_package;
4-bit ripple carry adder
library ieee;
entity adder4 is
port ( cin : in std_logic; x, y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0); cout : out std_logic);
end adder4;
begin
stage0: fulladd port map ( cin, x(0), y(0), s(0), c(1) );
stage3: fulladd port map ( c(3), x(3), y(3), s(3), cout );
end structure;
Generate Statements
Whenever we write structural VHDL code, we often create instances of a

particular component
– A multi-stage ripple carry adder made from a number of single-bit full
adders might be an example
• If we need to create a large number of instances of a component, a more
compact form is desired
• VHDL provides a feature called the for generate statement
– This statement provides a loop structure
4-bit ripple carry adder
library ieee;
entity adder4 is
port ( cin : in std_logic;
x, y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
cout : out std_logic);
end adder4;
begin
c(0) <= cin;
cout <= c(4);
g1: for i in 0 to 3 generate
stages: fulladd port map (c(i), x(i), y(i), s(i), c(i+1));
end generate;
end structure;
Process statement
• We have introduced several types of assignment statements
– All have the property that the order in which they appear in VHDL
code does not affect the meaning of the code
• Because of this property, these statements are called
concurrent assignment statements
• VHDL provides a second category of statements, sequential
assignment statements, for which the ordering of the
statements may affect the meaning of the code
– If-then-else and case statements are sequential
• VHDL requires that sequential assignment statements be
placed inside another statement, the process statement
Process statement
• The process statement, or simply process, begins with the PROCESS keyword,
followed by a parenthesized list of signals called the sensitivity list
– This list includes, at most, all the (input) signals used inside the process
– There may be no signals in the sensitivity list (i.e. the list may not exist)
– Generally the list includes all signals that can be used to “activate” the process
• Statements inside the process are evaluated in sequential order
– This is true from a simulation standpoint
– From a synthesized hardware point-of-view, multiple assignments to a single signal (variable)
generally implies multiplexing of the assignments to produce a single output
• Assignments made inside the process are not visible outside the process until all
statements in the process have been evaluated
– If there are multiple assignments to the same signal inside a process, only the last one has any visible
effect
Process Blocks
• The basic unit of behavioral descriptions. A process is considered a series of sequential statements which represents a single action
during simulation.
• Executed once at the beginning of simulation and then each time an event occurs on any signal in its sensitivity list and executed
until a wait statement or the end of the process is reached.
• All statements within a process are sequential, the execution time of a process can be thought of as
zero T.
Sensitivity
Architecture SEQ of DECODER 2x4 is
begin
list (equivalent to wait
MYPROCESS: process(A,B,ENABLE) on statements)
variable ABAR, BBAR:BIT;
Labels begin
Declarations
ABAR := not A; BBAR := not B;
if (ENABLE = ‘1’) then
Z(3) <= not (A and B); Sequential
Assign values Z(0) <= not (ABAR and BBAR); statements
to signal Z(2) <= not (A and BBAR);
drivers else Actual
Z<= ‘1111’; assignment
end if; of Signals
end process MYPROCESS;
end;
Process Rules
• If a process has a sensitivity list, then it can not contain a wait
statement
• A process with a sensitivity list is always triggered at time 0 because
all signals always have an initial event placed on them.
• A process without a sensitivity list is triggered at time 0 initially
• If a proc without a sensitivity list “falls out the bottom” then it loops
back to top until it hits a wait statement.
Interaction of Processes
READY
DATA PARALLEL OUT

Serial in Process RX Process MP
CLK ACK
RX: process
begin READY MP: process
READ_WORD(SERIAL_IN,CLK,DATA); begin
READY <= ‘1’; wait for 25 ns;
DATA PARALLEL_OUT <= DATA;
wait until ACK =‘1’;
READY <= ‘0’; ACK <= ‘1’,’0’ after 25 ns;
wait for 50 ns; wait until READY = ‘1’;
ACK end process MP;
end process RX;
READY
0 65 75 140 150
ACK 0 25 50 100 125 175 200ns

2-1 mux

begin
process (A,B,sel)
begin
if sel = '0' then
out <= A;
else
out <= B;
end if;
end process;
end behavior;
Priority encoder (IF-THEN-ELSE)
architecture behavior of priority is
begin
process (D)
begin
if D(3) = '1' then
Q <= "11";
elsif D(2) = '1' then
Q <= "10";
elsif D(1) = '1' then
Q <= "01";
else
Q <= "00";
end if;
end process;
z <= '0' when D = "0000" else '1';
end behavior;
Priority encoder (alternative)
architecture behavior of priority is
begin
process (w)
begin
y <= "00";
if w(1) = '1' then y <= "01" ; end if;
if w(2) = '1' then y <= "10" ; end if;
if w(3) = '1' then y <= "11" ; end if;
z <= '1';
if w = "0000" then z <= '0' ; end if;
end process;
end behavior;
Case Statement
A case statement is similar to a selected assignment statement in that the case
statement has a selection signal and includes WHEN clauses for various
valuations of the selection signal
– Begins with a CASE keyword

– Each WHEN clause specifies the statements that should be evaluated when the
selection signal has a specified
value
– The case statement must include a when clause for all valuations of the
selection signal
• Use the OTHERS keyword
2-1 mux with case

begin
process (A,B,sel)
begin
case sel is
when '0' => out <= A;
when others => out <= B;
end case;
end process;
end behavior;
2-1 binary decoder with case
architecture behavior of dec2to4 is
begin
process (w, en)
begin
if en = '1' then
case w is
when "00" => y <= "1000";
when "01" => y <= "0100";
when "10" => y <= "0010";
when others => y <= "0001";
end case ;
else
y <= "0000";
end if;
end process;
end behavior;
Small ALU Implementation using 2-1 decoder
entity DE1_SoC is
port
( 10
SW : in std_logic_vector(9 downto 0); Function
LEDR : out std_logic_vector(9 downto 0)
);
end DE1_SoC;
Small ALU Implementation using 2-1 decoder
architecture ppl_type of DE1_SoC is
begin
process(SW)
begin
LEDR(9 downto 3) <= (others => '0');
case SW(1 downto 0) is
when "00" =>
LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) + ('0' & SW(7 downto 6));
when "01" =>
LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) + (not ('0' & SW(7 downto 6))+"001");
when "10" =>
LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) and ('0' & SW(7 downto 6));
when "11" =>
LEDR(2 downto 0) <= ('0' & SW(9 downto 8)) xor ('0' & SW(7 downto 6));
when others =>
LEDR(2 downto 0) <= "XXX";
end case;
end process;
end;
Review of VHDL for Sequential Circuits
• Basic storage elements
– Structural design using library components
– Behavioral design: D latches and D flip-flops
• Options including
– Synchronous and asynchronous reset
– Multiplexed inputs
– Enable inputs
• Counters
• Shift Registers
• Arbitrary finite state machines (FSM) – next week?
– Mealy and Moore model designs – next week?
Structural VHDL Using a D flip-flop
package
library ieee;
library altera;
use altera.maxplus2.all;
entity flipflop is
port ( d, clock : in std_logic; reset_n,
preset_n : in std_logic; q : out std_logic);
end flipflop;
architecture structure of flipflop is
begin
dff_instance: dff port map (d,clock,reset_n,preset_n,q);
end structure;
Code for a gated D latch
library ieee;
entity latch is
port ( d, clk : in std_logic;q : out std_logic);
end latch;
architecture behavior of latch is
begin
process ( d, clk )
begin
if clk = '1' then
q <= d;
end if;
-- implied memory implementation
-- uses the last assigned value
end process;
end behavior;
Code for a D flip-flop
library ieee;
entity flipflop is
port ( d, clock : in std_logic;
q : out std_logic);
end flipflop;
architecture behavior of flipflop is
begin
process (clock)
begin
if clock'event and clock = '1' then
q <= d; Positive edge
end if; triggered
end process;
end behavior;
Code for a D flip-flop
library ieee;
entity flipflop is
port ( d, clock : in std_logic; q : out std_logic);
end flipflop;
begin
process (clock)
begin
if rising_edge(clock) then Use “falling edge”
q <= d; for negative going
end if; edge
end process;
Code for a D flip-flop (alternate)
library ieee;
entity flipflop is
port ( d, clock : in std_logic;
q : out std_logic );
end flipflop;
begin
process
begin
wait until clock'event and clock = '1';
q <= d;
end process;
end behavior;
D flip-flop with synchronous reset
library ieee;
entity flipflop is
port ( d, reset_n, clock : in std_logic;
q : out std_logic);
end flipflop;
begin
process
begin
if reset_n = '0' then
q <= '0';
else
q <= d;
end if;
end process;
D flip-flop with MUX input
library ieee;
entity muxdff is
port ( d0, d1, sel, clock : in std_logic;
q : out std_logic);
end muxdff;
architecture behavior of muxdff is
begin
process
begin
if sel = '0' then
q <= d0;
else
q <= d1;
end if;
end process;
end behavior;
D flip-flop with enable input
library ieee;
entity flipflop is
port ( enable, d, clk : in std_logic;q : out std_logic);
end flipflop;
begin
process(clk)
begin
if enable=‘0’ then null; This will be our preferred method
elsif rising_edge(clk) then for creating a D flip-flop or a
q <= d; multibit register with enable.
end if;
end process;
D flip-flop with asynchronous reset
library ieee;
entity flipflop is
port ( reset_n, d, clk : in std_logic;
q : out std_logic);
end flipflop;
begin
process(clk,reset_n)
begin
if reset_n =‘0’ then
q <= ‘0’;
This will be our preferred method
elsif rising_edge(clk) then
for creating a D flip-flop or a
q <= d;
multibit register with reset.
end if;
end process;
end behavior;
Counter Modeling with VHDL
Counters are simple examples of sequential circuits

• Counters can be modeled as arbitrary FSMs, but this is not the most
straightforward method of modeling these circuits
• Counters can be easily modeled using basic arithmetic expressions
• Options include:
– Arithmetic operations on UNSIGNED and SIGNED signals
– Use of the INTEGER data type
Four bit up counter
library ieee;
-- use numeric_std to include
-- signed and unsigned data types
use ieee.numeric_std.all;
entity upcount is
port ( clock, reset_n,e : in std_logic; q : out unsigned(3 downto 0));
end upcount;
Four bit up counter
architecture behavior of upcount is
signal count : unsigned(3 downto 0);
begin
process (clock,reset_n)
begin
if reset_n = '0' then
count <= "0000";
elsif (clock'event and clock = '1') then
if e = '1' then
count <= count + 1;
else
count <= count;
end if;
end if;
end process;
q <= count;
end behavior;
Up Counter Using INTEGER
library ieee;
entity count is
port( clock : in std_logic;
sload : in std_logic;
-- integer data types are a default size of 32 bits
-- use a range specifier to limit the number of bits
-- generated for the register (5 bits in this case)
data : in integer range 0 to 31;
result : out integer range 0 to 31;
end count;
Up Counter Using INTEGER
architecture rtl of count is
signal result_reg : integer range 0 to 31;
begin
process (clock)
begin
if (clock'event and clock = '1') then
if (sload = '1') then
result_reg <= data;
else
result_reg <= result_reg + 1;
end if;
end if;
end process;
result <= result_reg;
end rtl;
VHDL Shift Register Design
-- vhdl code for an 8-bit shift-left register with a
positive-
-- edge clock, asynchronous clear, serial in, and serial
out.
library ieee;
entity shift is
port(
-- clk is the clock for the shift operation
-- si is a serial input into the lsb of the shift register
-- clr is an asynchronous active high clear control signal
clk, si, clr : in std_logic;
-- so is a serial output from the msb of the shift register
so : out std_logic);
end shift;
VHDL Shift Register Design
architecture behavior of shift is
signal s_reg: std_logic_vector(7 downto 0);
begin
process(clk,clr)
begin
if(clr='1') then
s_reg <= "00000000";
elsif rising_edge(clk) then
s_reg <= s_reg (6 downto 0) & si;
end if;
end process;
so <= s_reg(7);
end behavior;
Rotate Register Example
use ieee.numeric_std.all;
entity rotatereg is
generic( width : integer := 8);
port(clk : in std_logic;
dir : in std_logic := '0';
reg_out : out std_logic_vector(width-1 downto 0));
end rotatereg;
architecture behavior of rotatereg is
signal reg : std_logic_vector(width-1 downto 0) := (0 => '1', others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
if (dir='0') then -- Rotate right if dir='0'
reg <= reg(0) & reg(width-1 downto 1);
else
reg <= reg(width-2 downto 0) & reg(width-1);
end if;
end if;
end process;
reg_out <= reg;
end behavior;
THESE TO BE MERGED WITH
PREVIOUS SLIDES!!!!
Sequential-Circuit Building Blocks

Constants & Packages
Mixing Description Styles

ECE 448 – FPGA and ASIC
Design with VHDL
Reading
Required
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 4, Regular Sequential Circuit
Recommended
• S. Brown and Z. Vranesic, Fundamentals of Digital

Logic with VHDL Design
Chapter 7, Flip-Flops, Registers, Counters,
and a Simple Processor
Design with VHDL
Behavioral Design Style:
Registers & Counters

Design with VHDL
VHDL Description Styles
VHDL Description
Styles
dataflow structural behavioral
Concurrent Components and Sequential statements

statements interconnects • Registers
• Shift registers
• Counters
synthesizable • State machines
and more
if you are careful
Design with VHDL
Processes in VHDL
• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful Statements
• Allow to define an arbitrary behavior that may be difficult to
represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to Be
Synthesized
• Use Processes Freely in Testbenches

Design with VHDL
Anatomy of a Process
OPTIONAL
[label:] PROCESS [(sensitivity list)]

[declaration part]
BEGIN
statement part
END PROCESS [label];

Design with VHDL
PROCESS with a SENSITIVITY LIST
• List of signals to which the process is

sensitive.
• Whenever there is an event on any of label: process (sensitivity list)
the signals in the sensitivity list, the
process fires. declaration part
• Every time the process fires, it will run begin
in its entirety. statement part
• WAIT statements are NOT ALLOWED end process;
in a processes with SENSITIVITY LIST.

Design with VHDL
Component Equivalent of a Process
clk y
w
priority: PROCESS (clk) a priority
z
BEGIN b
c
IF w(3) = '1' THEN
y <= "11" ; • All signals which appear on the left of signal assignment statement (<=) are outputs e.g.
y, z
• All signals which appear on the sensitivity list are inputs e.g. clk
ELSIF w(2) = '1' THEN • All signals which appear on the right of signal assignment statement (<=) or in logic
expressions are inputs e.g. w, a, b, c
y <= "10" ; • Note that not all inputs need to be included on the sensitivity list
ELSIF w(1) = c THEN

y <= a and b;
ELSE
z <= "00" ;
END IF ;
END PROCESS ;

Design with VHDL
Registers

Design with VHDL
D latch
Graphical symbol Truth table
Clock D Q(t+1)
D Q
0 – Q(t)
Clock 1 0 0
1 1 1
Timing diagram
t1 t2 t3 t4
Clock
D
Q
Time

Design with VHDL
D flip-flop
Graphical symbol Truth table
Clk D Q(t+1)
D Q
 0 0
Clock  1 1
0 – Q(t)
1 – Q(t)
Timing diagram
t1 t2 t3 t4
Clock
D
Q
Time

Design with VHDL
D latch
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
D Q
ENTITY latch IS
PORT ( D, Clock : IN STD_LOGIC ; Clock
Q : OUT STD_LOGIC) ;
END latch ;
ARCHITECTURE behavioral OF latch IS

BEGIN
PROCESS ( D, Clock )
BEGIN
IF Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral;

Design with VHDL
D flip-flop
LIBRARY ieee ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
END flipflop ;
ARCHITECTURE behavioral2 OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral2;

Design with VHDL
D flip-flop
LIBRARY ieee ;
D Q
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Clock
END flipflop ;
ARCHITECTURE behavioral OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;

Design with VHDL
D flip-flop with asynchronous reset
LIBRARY ieee ;
ENTITY flipflop_ar IS D Q
PORT ( D, Reset, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; Clock
END flipflop_ar ; Reset
ARCHITECTURE behavioral OF flipflop_ar IS

BEGIN
PROCESS ( Reset, Clock )
BEGIN
IF Reset = '1' THEN
Q <= '0' ;
ELSIF rising_edge(Clock) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
Design with VHDL
D flip-flop with synchronous reset
LIBRARY ieee ;
ENTITY flipflop_sr IS
PORT ( D, Reset, Clock : IN STD_LOGIC ;
D Q
END flipflop_sr ;
Clock
ARCHITECTURE behavioral OF flipflop_sr IS Reset
BEGIN
PROCESS(Clock)
BEGIN
IF Reset = '1' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END behavioral ;

Design with VHDL
Asychronous vs. Synchronous
• In the IF loop, asynchronous items are

• Before the rising_edge(Clock) statement
• In the IF loop, synchronous items are
• After the rising_edge(Clock) statement

Design with VHDL
8-bit register with asynchronous reset
LIBRARY ieee ;
ENTITY reg8 IS
PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Reset, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;
ARCHITECTURE behavioral OF reg8 IS

BEGIN
PROCESS ( Reset, Clock ) 8 Reset 8
BEGIN D Q
IF Reset = '1' THEN
Q <= "00000000" ;
ELSIF rising_edge(Clock) THEN Clock
Q <= D ;
reg8
END IF ;
END PROCESS ;
END
ECE 448 – FPGA andbehavioral
ASIC ;`
Design with VHDL
N-bit register with asynchronous reset
LIBRARY ieee ;
ENTITY regn IS
GENERIC ( N : INTEGER := 16 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Reset, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE behavioral OF regn IS

BEGIN N N
Reset
PROCESS ( Reset, Clock )
BEGIN D Q
IF Reset = '1' THEN
Q <= (OTHERS => '0') ;
ELSIF rising_edge(Clock) THEN Clock
Q <= D ;
END IF ; regn
END PROCESS ;
END behavioral ;
Design with VHDL
A word on generics
• Generics are typically integer values
• In this class, the entity inputs and outputs should be
std_logic or std_logic_vector
• But the generics can be integer
• Generics are given a default value
• GENERIC ( N : INTEGER := 16 ) ;
• This value can be overwritten when entity is instantiated as a
component
• Generics are very useful when instantiating an often-used
component
• Need a 32-bit register in one place, and 16-bit register in
another
• Can use the same generic code, just configure them
differently

Design with VHDL
Use of OTHERS
OTHERS stand for any index value that has

not been previously mentioned.
Q <= “00000001” can be written as Q <= (0 => ‘1’, OTHERS =>

‘0’)
Q <= “10000001” can be written as Q <= (7 => ‘1’, 0 => ‘1’, OTHERS => ‘0’)
or Q <= (7 | 0 => ‘1’, OTHERS => ‘0’)
Q <= “00011110” can be written as Q <= (4 downto 1=> ‘1’, OTHERS => ‘0’)

Design with VHDL
in VHDL-93
U1: ENTITY work.regn(behavioral)

GENERIC MAP (N => 4)
PORT MAP (D => z ,
Reset => reset ,
Clock => clk,
Q => t );

Design with VHDL
in VHDL-87
U1: regn GENERIC MAP (N => 4)

PORT MAP (D => z ,
Reset => reset ,
Clock => clk,
Q => t );

Design with VHDL
N-bit register with enable
LIBRARY ieee ;
ENTITY regne IS
Enable, Clock : IN STD_LOGIC ;
END regne ;
ARCHITECTURE behavioral OF regne IS

BEGIN
PROCESS (Clock) N Enable N
BEGIN D Q
IF Enable = '1' THEN
Q <= D ;
Clock
END IF ;
END IF; regn
END PROCESS ;
END behavioral ;
Design with VHDL
Implementing two registers in a single process
Enf Enf
Cout_tmp En Cout V_tmp En

V
D Q D Q
Clk Clk
Reset Reset

Design with VHDL
PROCESS (Clk, Reset)

BEGIN
IF Reset= '1' THEN
Cout <= '0';
V <= '0';
ELSIF rising_edge(Clk) THEN
IF Enf = '1' THEN
Cout <= Cout_tmp ;
V <= V_tmp;
END IF ;
END IF;
END PROCESS ;

Design with VHDL
EnC EnV
Cout_tmp En Cout V_tmp En

V
D Q D Q
Clk Clk
Reset Reset

Design with VHDL
PROCESS (Clk, Reset)

BEGIN
IF Reset = '1' THEN
Cout <= ‘0’;
V <= '0';
ELSIF rising_edge(Clk) THEN
IF EnC = '1' THEN
Cout <= Cout_tmp ;
END IF ;
IF EnV = '1' THEN
V <= V_tmp;
END IF ;
END IF;
END PROCESS ;

Design with VHDL
Counters

Design with VHDL
2-bit up-counter with synchronous reset
LIBRARY ieee ;
USE ieee.std_logic_unsigned.all ;
ENTITY upcount IS
PORT ( Reset, Clock : IN STD_LOGIC ;
END upcount ;
ARCHITECTURE behavioral OF upcount IS

SIGNAL Count : std_logic_vector(1 DOWNTO 0);
BEGIN
Reset 2
upcount: PROCESS ( Clock )
Q
BEGIN
upcount
IF Reset = '1' THEN
Count <= "00" ;
Clock
ELSE
Count <= Count + 1 ;
END IF ;
END IF;
END PROCESS;
Q <= Count;
END behavioral;
Design with VHDL
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee ;
ENTITY upcount_ar IS
PORT ( Clock, Reset, Enable : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;
END upcount_ar ;
Enable 4
Q
Clock
upcount
Reset

Design with VHDL
4-bit up-counter with asynchronous reset (2)
ARCHITECTURE behavioral OF upcount _ar IS
SIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Reset )
BEGIN
IF Reset = '1' THEN
Count <= "0000" ;
ELSIF rising_edge(Clock) THEN
Count <= Count + 1 ;
END IF ; Enable 4
END IF ; Q
END PROCESS ;
Q <= Count ; Clock
END behavioral ; upcount
Resetn

Design with VHDL
Shift Registers

Design with VHDL
Shift register – internal structure
Q(3) Q(2) Q(1) Q(0)
Sin
D Q D Q D Q D Q
Clock
Enable

Design with VHDL
Shift Register
Load
With Parallel Load
D(3)
D(2) D(1) D(0)
Sin
D Q D Q D Q D Q
Clock
Enable
Q(3) Q(2) Q(1) Q(0)

Design with VHDL
4-bit shift register with parallel load (1)
LIBRARY ieee ;
ENTITY shift4 IS
PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
END shift4 ;
4 Enable 4
D Q
Load
Sin
shift4
Clock
Design with VHDL
4-bit shift register with parallel load (2)
ARCHITECTURE behavioral OF shift4 IS
SIGNAL Qt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN 4 Enable 4
PROCESS (Clock) D Q
BEGIN Load
Sin
IF Enable = ‘1’ THEN shift4
IF Load = '1' THEN Clock
Qt <= D ;
ELSE
Qt <= Sin & Qt(3 downto 1);
END IF;
END IF ;
END PROCESS ;
Q <= Qt;
END behavioral ;

Design with VHDL
N-bit shift register with parallel load (1)
LIBRARY ieee ;
ENTITY shiftn IS
Enable : IN STD_LOGIC ;
Load : IN STD_LOGIC ;
Sin : IN STD_LOGIC ;
Clock : IN STD_LOGIC ;
END shiftn ;
N Enable N
D Q
Load
Sin
shiftn
Clock
Design with VHDL
N-bit shift register with parallel load (2)
ARCHITECTURE behavioral OF shiftn IS
SIGNAL Qt: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN N N
Enable
PROCESS (Clock)
D Q
BEGIN
IF rising_edge(Clock) THEN Load
IF Enable = ‘1’ THEN Sin
shiftn
IF Load = '1' THEN
Clock
Qt <= D ;
ELSE
Qt <= Sin & Qt(N-1 downto 1);
END IF;
END IF ;
END PROCESS ;
Q <= Qt;
END behavior al;

Design with VHDL
Generic Component
Instantiation

Design with VHDL
N-bit register with enable
LIBRARY ieee ;
ENTITY regne IS
END regne ;
ARCHITECTURE Behavior OF regne IS

BEGIN
PROCESS (Clock) N Enable N
BEGIN D Q
IF (Clock'EVENT AND Clock = '1' ) THEN
Q <= D ;
Clock
END IF ;
END IF; regne
END PROCESS ;
END Behavior ;
Design with VHDL
Circuit built of medium scale components
s(0)
r(0) 0 p(0) En
r(1) 1
w0 q(1) Enable
p(1) y1 w y
q(0) 1 3 z(3) t(3)
r(2) w1
p(2) y0 w y
r(3) w2 0 2 z(2) t(2)
ena D Q
z y
w3 1
priority
z(1) t(1)
r(4) 0 p(3) y
En 0 z(0) t(0)
dec2to4 regne
r(5) 1
Clk Clock
s(1)
Design with VHDL
Structural description – example (1)
VHDL-93
LIBRARY ieee ;
ENTITY priority_resolver IS
PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;
ARCHITECTURE structural OF priority_resolver IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;

Design with VHDL
VHDL-93
BEGIN
u1: ENTITY work.mux2to1(dataflow)

PORT MAP (w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(2) <= r(3);
u2: ENTITY work.mux2to1(dataflow)

PORT MAP (w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));
u3: ENTITY work.priority(dataflow)

PORT MAP (w => p,
y => q,
z => ena);

Design with VHDL
VHDL-93
u4: ENTITY work.dec2to4(dataflow)
PORT MAP (w => q,
En => ena,
y => z);
u5: ENTITY work.regne(behavioral)
GENERIC MAP (N => 4)
PORT MAP (D => z ,
Enable => En ,
Clock => Clk,
Q => t );
END structural;

Design with VHDL
VHDL-87
LIBRARY ieee ;
ENTITY priority_resolver IS
PORT (r: IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver;
ARCHITECTURE structural OF priority_resolver IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;

Design with VHDL
VHDL-87
COMPONENT mux2to1
PORT (w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
COMPONENT priority
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END COMPONENT ;
COMPONENT dec2to4
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;

Design with VHDL
VHDL-87
COMPONENT regne
END COMPONENT ;

Design with VHDL
VHDL-87
BEGIN
u1: mux2to1 PORT MAP (w0 => r(0) ,

w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(2) <= r(3);
u2: mux2to1 PORT MAP (w0 => r(4) ,

w1 => r(5),
s => s(1),
f => p(3));
u3: priority PORT MAP (w => p,

y => q,
z => ena);
u4: dec2to4 PORT MAP (w => q,

En => ena,
y => z);

Design with VHDL
VHDL-87
u5: regne GENERIC MAP (N => 4)
PORT MAP (D => z ,
Enable => En ,
Clock => Clk,
Q => t );
END structural;

Design with VHDL
Constants

Design with VHDL
Constants
Syntax:
CONSTANT name : type := value;
Examples:
CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100";

CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4";
CONSTANT counter_width : INTEGER := 16;
CONSTANT buffer_address : INTEGER := 16#FFFE#;
CONSTANT clk_period : TIME := 20 ns;
CONSTANT strobe_period : TIME := 333.333 ms;
Design with VHDL
Constants - features
Constants can be declared in a
PACKAGE, ARCHITECTURE, ENTITY
When declared in a PACKAGE, the constant

is truly global, for the package can be used
in several entities.
When declared in an ARCHITECTURE, the

constant is local, i.e., it is visible only within this architecture.
When declared in an ENTITY declaration, the constant

can be used in all architectures associated with this entity.
Example of package
library ieee;
package alu_pkg is
constant OPCODE_NOR : std_logic_vector(2 downto 0) := "000";

constant OPCODE_NAND : std_logic_vector(2 downto 0) := "001";
constant OPCODE_XOR : std_logic_vector(2 downto 0) := "010";
constant OPCODE_UADD : std_logic_vector(2 downto 0) := "011";
constant OPCODE_SADD : std_logic_vector(2 downto 0) := "100";
constant OPCODE_SSUB : std_logic_vector(2 downto 0) := "101";
constant OPCODE_UMUL : std_logic_vector(2 downto 0) := "110";
constant OPCODE_SMUL : std_logic_vector(2 downto 0) := "111";
end alu_pkg;
Using objects from a package
library ieee;
library work;
use work.alu_pkg.all;
entity alu_comb is
…………..
Mixing Description Styles
Inside of an Architecture

Design with VHDL
VHDL Description Styles
VHDL Description
Styles

• Shift registers
• Counters
synthesizable • State machines
Mixed Style Modeling
architecture ARCHITECTURE_NAME of ENTITY_NAME is
• Here you can declare signals, constants, types, etc.
begin
Concurrent statements:
• Simple signal assignment
• Conditional signal assignment
• Selected signal assignment
Component instantiation statement
Process statement
• inside process you can use only sequential
statements
end ARCHITECTURE_NAME;
PRNG Example (1)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.prng_pkg.all;
ENTITY PRNG IS
PORT( Coeff : in std_logic_vector(4 downto 0);
Load_Coeff : in std_logic;
Seed : in std_logic_vector(4 downto 0);
Init_Run : in std_logic;
Clk : in std_logic;
Current_State : out std_logic_vector(4 downto 0));
END PRNG;
ARCHITECTURE mixed OF PRNG is

signal Ands : std_logic_vector(4 downto 0);
signal Sin : std_logic;
signal Coeff_Q : std_logic_vector(4 downto 0);
signal Shift5_Q : std_logic_vector(4 downto 0);
PRNG Example (2)
BEGIN
-- Data Flow
Sin <= Ands(0) XOR Ands(1) XOR Ands(2) XOR Ands(3) XOR Ands(4);
Current_State <= Shift5_Q;
Ands <= Coeff_Q AND Shift5_Q;
-- Behavioral
Coeff_Reg: PROCESS(Clk)
BEGIN
IF rising_edge(Clk) THEN
IF Load_Coeff = '1' THEN
Coeff_Q <= Coeff;
END IF;
END IF;
END PROCESS;
-- Structural
Shift5_Reg : ENTITY work.Shift5(behavioral) PORT MAP ( D => Seed,
Load => Init_Run,
Sin => Sin,
Clock => Clk,
Q => Shift5_Q);
END mixed;
Sequential Logic Synthesis
for
Beginners

Design with VHDL
For Beginners
Use processes with very simple structure only
to describe
- registers
- shift registers
- counters
- state machines.
Use examples discussed in class as a template.
Create generic entities for registers, shift registers, and
counters, and instantiate the corresponding components in
a higher level circuit using GENERIC MAP PORT MAP.
Supplement sequential components with
combinational logic described using concurrent statements.
Sequential Logic Synthesis
for
Intermediates

Design with VHDL
For Intermmediates
1. Use Processes with IF and CASE statements only. Do not use
LOOPS or VARIABLES.
2. Sensitivity list of the PROCESS should include only signals
that can by themsleves change the outputs of the sequential
circuit (typically, clock and asynchronous set or reset)
3. Do not use PROCESSes without sensitivity list
(they can be synthesizable, but make simulation inefficient)
For Intermmediates (2)
Given a single signal, the assignments to this signal should
only be made within a single process block in order to avoid
possible conflicts in assigning values to this signal.
Process 1: PROCESS (a, b)

BEGIN
y <= a AND b;
END PROCESS;
Process 2: PROCESS (a, b)

BEGIN
y <= a OR b;
END PROCESS;
THESE TO BE MERGED WITH
PREVIOUS SLIDES !!!!
Combinational-Circuit Building Blocks
Data Flow Modeling of

Combinational Logic

Design with VHDL
Reading
Required
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3, RT-level combinational circuit
Sections 3.1, 3.2, 3.3, 3.6, 3.7.1, 3.7.3.
Recommended
• S. Brown and Z. Vranesic, Fundamentals of Digital
Logic with VHDL Design
Chapter 6, Combinational-Circuit Building Blocks
Chapter 5.5, Design of Arithmetic Circuits Using
CAD Tools
Design with VHDL
Types of VHDL Description
(Modeling Styles)

Design with VHDL
Types of VHDL Description
VHDL Descriptions
• Testbenches

• State machines
• Instruction decoders
Subset most suitable for synthesis

Design with VHDL
Synthesizable VHDL
VHDL code
Dataflow VHDL
synthesizable
VHDL code
Dataflow VHDL
synthesizable

Design with VHDL
Data-Flow VHDL
Concurrent Statements
• concurrent signal assignment
()
• conditional concurrent signal assignment

(when-else)
• selected concurrent signal assignment

(with-select-when)

Design with VHDL
Concurrent signal assignment
<=
target_signal <= expression;

Design with VHDL
Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

Design with VHDL
Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

Design with VHDL
Modeling Wires and Buses

Design with VHDL
Signals
SIGNAL a : STD_LOGIC;
a
1 wire
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);
b
8 bus

Design with VHDL
Merging wires and buses
a
4
10
b 5
d = a || b || c
c
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;

Design with VHDL
Splitting buses
a = d9..6
4
10
d 5 b = d5..1
c = d0
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);

b <= d(5 downto 1);
c <= d(0);

Design with VHDL
Combinational-Circuit
Building Blocks

Design with VHDL
Fixed Shifters & Rotators

Design with VHDL
Fixed Logical Shift Right in VHDL
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL C: STD_LOGIC_VECTOR(3 DOWNTO 0);
4
A(3) A(2) A(1) A(0)
A
A
>>1
C L
4 C
‘0’ A(3) A(2) A(1)
C = '0' & A(3 downto 1);

Design with VHDL
Fixed Arithmetic Shift Right in VHDL
4
A(3) A(2) A(1) A(0)
A
A
>>1
C A
4 C
A(3) A(3) A(2) A(1)
C = A(3) & A(3 downto 1);

Design with VHDL
Fixed Logical Shift Left in VHDL
4
A(3) A(2) A(1) A(0)
A
A
<<1
C L
4 C
A(2) A(1) A(0) ‘0’
C = A(2 downto 0) & '0';

Design with VHDL
Fixed Rotation Left in VHDL
4
A(3) A(2) A(1) A(0)
A
A
<<< 1
C
4 C
A(2) A(1) A(0) A(3)
C = A(2 downto 0) & A(3);

Design with VHDL
Variable Rotators

Design with VHDL
8-bit Variable Rotator Left
A
3
B A <<< B
C
8
To be covered during one of the future classes

Design with VHDL
Gates

Design with VHDL
Basic Gates – AND, OR, NOT
x1
x2
x1
x1 ×
x2 x1 ×
x2 ×
×
xn
x2
xn
(a) AND gates
x1
x2
x1
x1 + x2 x1+ x2+ + xn
x2
xn
(b) OR gates
x x
(c) NOT gate

Design with VHDL
Basic Gates – NAND, NOR
x1
x2
x1
x 1  x 2 x 1  x 2  …
  x n
x2
xn
(a) NAND gates
x1
x2
x1
x1 + x2 x 1 + x 2 +… + x n
x2
xn
(b) NOR gates

Design with VHDL
DeMorgan’s Theorem and other symbols
for NAND, NOR
x1
x1 x1
x2 x2
x2
(a) x1 x2 = x1 + x2
x1
x1 x1
x2 x2
x2
(b) x1 + x2 = x1 x2

Design with VHDL
Basic Gates – XOR
x1 x2 f = x1 x2
0 0 0
0 1 1
x1
1 0 1 f = x1 x2
x2
1 1 0
(a) Truth table (b) Graphical symbol
x1
x2
f = x1 x2
(c) Sum-of-products implementation

Design with VHDL
Basic Gates – XNOR
x1 x2 f = x1 x2
0 0 1
0 1 0
x1
1 0 0 f = x1 x2 = x1 . x2
x2
1 1 1
(a) Truth table (b) Graphical symbol
x1
x2
f = x1 x2
(c) Sum-of-products implementation

Design with VHDL
Data-flow VHDL: Example
x
y s
cin
cout
ECE 448 – FPGA and ASIC Design with VHDL

Data-flow VHDL: Example (1)
LIBRARY ieee ;
ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

Design with VHDL
Data-flow VHDL: Example (2)
ARCHITECTURE dataflow OF fulladd IS

BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;

Design with VHDL
Logic Operators
• Logic operators
and or nand nor xor not xnor
• Logic operators precedence only in VHDL-93

Highest
not
and or nand nor xor xnor
Lowest

Design with VHDL
No Implied Precedence
Wanted: y = ab + cd
Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
equivalent to
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;

Design with VHDL
Multiplexers

Design with VHDL
2-to-1 Multiplexer
s
s f
w
0 0 w
f 0 0
w
1 1 1 w
1
(a) Graphical symbol (b) Truth table
VHDL: f <= w0 WHEN s = '0' ELSE w1 ;

or
f <= w1 WHEN s = ‘1' ELSE w0 ;

Design with VHDL
VHDL code for a 2-to-1 Multiplexer Entity
LIBRARY ieee ;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
END mux2to1 ;
ARCHITECTURE dataflow OF mux2to1 IS

BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;

Design with VHDL
Cascade of two multiplexers
w 0
3
0
w 1 y
2 w
1 1
s2
s1
VHDL:
f <= w1 WHEN s1 = ‘1' ELSE
w2 WHEN s2 = ‘1’ ELSE
w3 ;

Design with VHDL
VHDL design entity implementing
a cascade of two multiplexers
LIBRARY ieee ;
ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s2 : IN STD_LOGIC ;
END mux_cascade ;

BEGIN
f <= w1 WHEN s1 = ‘1' ELSE
w2 WHEN s2 = ‘1’ ELSE
w3 ;
END dataflow ;
Design with VHDL
Operators
• Relational operators
= /= < <= > >=
• Logic and relational operators precedence

Highest not
= /= < <= > >=
and or nand nor xor xnor
Lowest

Design with VHDL
Priority of logic and relational operators
compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …

Design with VHDL
4-to-1 Multiplexer
(a) Graphic symbol (b) Truth table
s
s 0
s s f
s 1 0
1
w 0 0 w
0 00 0
w 0 1 w
1 01 1
f
w 1 0 w
2 10 2
w 11 1 1 w
3 3
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
Design with VHDL
VHDL code for a 4-to-1 Multiplexer entity
LIBRARY ieee ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
END mux4to1 ;

BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END dataflow ;

Design with VHDL
Decoders

Design with VHDL
2-to-4 Decoder
(b) Graphical
symbol
(a) Truth table w y
w 1 3
w y
En w w y y y y 0 2
1 0 3 2 1 0 y
y
1
1 0 0 0 0 0 1 y
En 0
1 0 1 0 0 1 0
1 1 0 0 1 0 0 Enw <= En & w ;
1 1 1 1 0 0 0 WITH Enw SELECT
y <= "0001" WHEN "100",
0 x x 0 0 0 0 "0010" WHEN "101",
"0100" WHEN "110",
"1000" WHEN "111",
"0000" WHEN OTHERS ;
Design with VHDL
VHDL code for a 2-to-4 Decoder entity
LIBRARY ieee ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
"1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;
Design with VHDL
Encoders

Design with VHDL
Priority Encoder
w0
y0
w1 y
w y1
w2 y <= "11" WHEN w(3) = '1' ELSE
w3 z "10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
w3 w2 w1 w0 y1 y0 z z <= '0' WHEN w = "0000" ELSE '1' ;
0 0 0 0 d d 0
0 0 0 1 0 0 1
0 0 1 - 0 1 1
0 1 - - 1 0 1
1 - - - 1 1 1

Design with VHDL
VHDL code for a Priority Encoder entity
LIBRARY ieee ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ARCHITECTURE dataflow OF priority IS

BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;
Design with VHDL
Adders

Design with VHDL
16-bit Unsigned Adder
16 16
X Y
Cout + Cin
S
16

Design with VHDL
Operations on Unsigned Numbers
For operations on unsigned numbers
USE ieee.std_logic_unsigned.all
and
signals of the type
STD_LOGIC_VECTOR
OR
USE ieee.numeric_std.all
and
signals of the type
UNSIGNED
and conversion functions:
std_logic_vector(), unsigned()

Design with VHDL
VHDL code for a 16-bit Unsigned Adder
LIBRARY ieee ;
ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Cout : OUT STD_LOGIC ) ;
END adder16 ;
ARCHITECTURE dataflow OF adder16 IS

SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
END dataflow ;
Design with VHDL
Addition of Unsigned Numbers (1)
LIBRARY ieee ;
USE ieee.numeric_std.all ;
ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Cout : OUT STD_LOGIC ) ;
END adder16 ;

Design with VHDL
SIGNAL Xu : UNSIGNED(15 DOWNTO 0);
SIGNAL Yu: UNSIGNED(15 DOWNTO 0);
SIGNAL Su : UNSIGNED(16 DOWNTO 0) ;
BEGIN
Xu <= unsigned(X);
Yu <= unsigned(Y);
Su <= ('0' & Xu) + Yu + unsigned(std_logic_vector' ('0' & Cin)) ;
S <= std_logic_vector(Su(15 DOWNTO 0)) ;
Cout <= Su(16) ;
END dataflow ;

Design with VHDL
signal Sum: STD_LOGIC_VECTOR(16 DOWNTO 0) ;
BEGIN
Sum <= std_logic_vector( unsigned('0' & X) + unsigned(Y)
+ unsigned(std_logic_vector' ('0' & Cin)) ) ;
S <= Sum(15 downto 0);
Cout <= Sum(16) ;
END dataflow ;

Design with VHDL
Operations on Signed Numbers
For operations on signed numbers
USE ieee.numeric_std.all,
signals of the type
SIGNED,
and conversion functions:
std_logic_vector(), signed()
OR
USE ieee.std_logic_signed.all
and signals of the type
STD_LOGIC_VECTOR
Design with VHDL
Signed and Unsigned Types
Behave exactly like

STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

Design with VHDL
Multipliers

Design with VHDL
Unsigned vs. Signed Multiplication
Unsigned Signed
1111 15 1111 -1
x 1111 x 15 x 1111 x -1
11100001 225 00000001 1

Design with VHDL
8x8-bit Unsigned Multiplier
8 8
a b
*
c U
16

Design with VHDL
Multiplication of unsigned numbers
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity multiply is
port(
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
c : out STD_LOGIC_VECTOR(15 downto 0)
);
end multiply;
architecture dataflow of multiply is

begin
c <= a * b;
end dataflow;

Design with VHDL
8x8-bit Signed Multiplier
8 8
a b
*
c S
16

Design with VHDL
Multiplication of signed numbers
LIBRARY ieee;
USE ieee.std_logic_signed.all ;
entity multiply is
port(
c : out STD_LOGIC_VECTOR(15 downto 0)
);
end multiply;

begin
c <= a * b;
end dataflow;

Design with VHDL
8x8-bit Unsigned and Signed Multiplier
8 8
a b
*
cu cs
16 16

Design with VHDL
Multiplication of signed and unsigned numbers
LIBRARY ieee;
USE ieee.numeric_std.all ;
entity multiply is
port(
cu : out STD_LOGIC_VECTOR(15 downto 0);
cs : out STD_LOGIC_VECTOR(15 downto 0)
);
end multiply;

begin
-- signed multiplication
cs <= STD_LOGIC_VECTOR(SIGNED(a)*SIGNED(b));
-- unsigned multiplication
cu <= STD_LOGIC_VECTOR(UNSIGNED(a)*UNSIGNED(b));
end dataflow;

Design with VHDL
Comparators

Design with VHDL
4-bit Number Comparator
4
A
4
A>B AgtB
B
AgtB <= '1' WHEN A > B ELSE '0' ;

Design with VHDL
VHDL code for a 4-bit Unsigned Number Comparator
entity
LIBRARY ieee ;
ENTITY compare IS
PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
AgtB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE dataflow OF compare IS

BEGIN
END dataflow ;

Design with VHDL
VHDL code for a 4-bit Signed Number Comparator
entity
LIBRARY ieee ;
USE ieee.std_logic_signed.all ;
ENTITY compare IS
PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
AgtB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE dataflow OF compare IS

BEGIN
END dataflow ;

Design with VHDL
Buffers

Design with VHDL
Tri-state Buffer
e
x f
e= 0
(a) A tri-state buffer x f
e x f e= 1
x f
0 0 Z
0 1 Z
1 0 0 (b) Equivalent circuit
1 1 1
(c) Truth table

Design with VHDL
Four types of Tri-state Buffers
e e
x f x f
f <= x WHEN (e(a)

= '1') ELSE 'Z'; f <= not x WHEN
(b) (e = '1') ELSE 'Z';
e e
x f x f
f <= x WHEN (e(c)

= '0') ELSE 'Z'; (d) (e = '0') ELSE 'Z';
f <= not x WHEN
Design with VHDL
Tri-state Buffer entity (1)
LIBRARY ieee;
ENTITY tri_state IS
PORT ( e: IN STD_LOGIC;
x: IN STD_LOGIC;
f: OUT STD_LOGIC
);
END tri_state;

Design with VHDL
Tri-state Buffer entity (2)
ARCHITECTURE dataflow OF tri_state IS

BEGIN
f <= x WHEN (e = ‘1’) ELSE ‘Z’;
END dataflow;

Design with VHDL
ROM

Design with VHDL
ROM 8x16 example (1)
Addr
8x16
ROM
Dout
16
C
Design with VHDL
LIBRARY ieee;
USE ieee.numeric_std.all;
ENTITY rom IS
PORT (
Addr : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END rom;
ARCHITECTURE dataflow OF rom IS
SIGNAL temp: INTEGER RANGE 0 TO 7;
TYPE vector_array IS ARRAY (0 to 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
CONSTANT memory : vector_array :=
( X”800A",
X"D459",
X"A870",
X"7853",
X"650D",
X"642F",
X"F742",
X"F548");
BEGIN
temp <= to_integer(unsigned(Addr));

Dout <= memory(temp);
END dataflow;
Describing
Combinational Logic
Using
Dataflow Design Style

Design with VHDL
MLU Example

Design with VHDL
MLU Block Diagram
MUX_0
0 A1
A
1
MUX_4_1
IN0 Y1
MUX_1
NEG_A IN1 0
MUX_2 IN2 OUTPUT Y
1
IN3 SEL0
SEL1
NEG_Y
0 B1
B
1
L1 L0
MUX_3
NEG_B
MLU: Entity Declaration
LIBRARY ieee;
ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A: IN STD_LOGIC;
B: IN STD_LOGIC;
L1 : IN STD_LOGIC;
L0 : IN STD_LOGIC;
Y: OUT STD_LOGIC
);
END mlu;

Design with VHDL
MLU: Architecture Declarative Section
ARCHITECTURE mlu_dataflow OF mlu IS
SIGNAL A1 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL MUX_0 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

Design with VHDL
MLU - Architecture Body
BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE
A;
B1<= NOT B WHEN (NEG_B='1') ELSE
B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;
MUX_0 <= A1 AND B1;

MUX_1 <= A1 OR B1;
MUX_2 <= A1 XOR B1;
MUX_3 <= A1 XNOR B1;
L <= L1 & L0;
with (L) select

Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;
END mlu_dataflow;

Design with VHDL
Logic Implied Most Often by
Conditional and Selected
Concurrent Signal
Assignments

Design with VHDL
Data-flow VHDL
Major instructions
Concurrent statements
• concurrent signal assignment ()
(when-else)
(with-select-when)

Design with VHDL
Conditional concurrent signal assignment
When - Else
. . .
valueN;

Design with VHDL
Most often implied structure
When - Else
. . .
valueN;
Value N 0
1
.… … 0
Value N-1 1 0
Target Signal
1
Value 2
Value 1
Condition N-1
Condition 2
Condition 1
Design with VHDL
Data-flow VHDL
Major instructions
Concurrent statements
• concurrent signal assignment ()
(when-else)
(with-select-when)

Design with VHDL
Selected concurrent signal assignment
With –Select-When
. . .

Design with VHDL
Most Often Implied Structure
With –Select-When
. . .
expression1 choices_1
expression2 choices_2
target_signal
expressionN choices_N
choice expression
Design with VHDL
Allowed formats of choices_k
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS

Design with VHDL
Allowed formats of choice_k - example
WITH sel SELECT

y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;

Design with VHDL
when-else vs. with-select-when (1)
"when-else" should be used when:

1) there is only one condition (and thus, only one
else), as in the 2-to-1 MUX
2) conditions are independent of each other (e.g.,
they test values of different signals)
3) conditions reflect priority (as in priority encoder);
one with the highest priority need to be tested first.

Design with VHDL
when-else vs. with-select-when (2)
"with-select-when" should be used when there is

1) more than one condition
2) conditions are closely related to each other (e.g.,
represent different ranges of values of the same
signal)
3) all conditions have the same priority (as in the 4-to-
1 MUX).

Design with VHDL
Non-synthesizable VHDL

Design with VHDL
Delays
Delays are not synthesizable
Statements, such as
wait for 5 ns
a <= b after 10 ns
will not produce the required delay, and
should not be used in the code intended
for synthesis.

Design with VHDL
Initializations
Declarations of signals (and variables)
with initialized values, such as
SIGNAL a : STD_LOGIC := ‘0’;
cannot be synthesized, and thus should
be avoided.
If present, they will be ignored by the
synthesis tools.
Use set and reset signals instead.

Design with VHDL
Dual-edge triggered register/counter (1)
In FPGAs register/counter can change only
at either rising (default) or falling edge of the
clock.
Dual-edge triggered clock is not synthesizable

correctly, using either of the descriptions
provided below.

Design with VHDL
PROCESS (clk)
BEGIN
IF (clk’EVENT AND clk=‘1’ ) THEN
counter <= counter + 1;
ELSIF (clk’EVENT AND clk=‘0’ ) THEN
END IF;
END PROCESS;

Design with VHDL
PROCESS (clk)
BEGIN
IF (clk’EVENT) THEN
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
END PROCESS;

Design with VHDL

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ELE432

ADVANCED DIGITAL DESIGN

• The assignment of a waveform value to a signal is referred to as

VHDL provides several types of statements that can be used to

A selected signal assignment allows a signal to be assigned

architecture Behavioral of Priority_Encoder_VHDL is

library ieee ; library ieee;

Whenever we write structural VHDL code, we often create instances of a

DATA PARALLEL OUT

ACK 0 25 50 100 125 175 200ns

architecture behavior of mux2to1 is

– Begins with a CASE keyword

architecture behavior of mux2to1 is

Counters are simple examples of sequential circuits

Sequential-Circuit Building Blocks

Mixing Description Styles

• S. Brown and Z. Vranesic, Fundamentals of Digital

ECE 448 – FPGA and ASIC

dataflow structural behavioral

Concurrent Components and Sequential statements

ECE 448 – FPGA and ASIC

[label:] PROCESS [(sensitivity list)]

ECE 448 – FPGA and ASIC

• List of signals to which the process is

ECE 448 – FPGA and ASIC

ELSIF w(1) = c THEN

ECE 448 – FPGA and ASIC

ECE 448 – FPGA and ASIC

ECE 448 – FPGA and ASIC

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF latch IS

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral2 OF flipflop IS

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF flipflop IS

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF flipflop_ar IS

ECE 448 – FPGA and ASIC

• In the IF loop, asynchronous items are

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF reg8 IS

ARCHITECTURE behavioral OF regn IS

ECE 448 – FPGA and ASIC

OTHERS stand for any index value that has

Q <= “00000001” can be written as Q <= (0 => ‘1’, OTHERS =>

ECE 448 – FPGA and ASIC

U1: ENTITY work.regn(behavioral)

ECE 448 – FPGA and ASIC

U1: regn GENERIC MAP (N => 4)

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF regne IS

Cout_tmp En Cout V_tmp En

ECE 448 – FPGA and ASIC

PROCESS (Clk, Reset)

ECE 448 – FPGA and ASIC

Cout_tmp En Cout V_tmp En

ECE 448 – FPGA and ASIC

PROCESS (Clk, Reset)

ECE 448 – FPGA and ASIC

ECE 448 – FPGA and ASIC

ARCHITECTURE behavioral OF upcount IS

ECE 448 – FPGA and ASIC

ECE 448 – FPGA and ASIC