Use ieee.std_logic_arith.

all;
Use ieee.std_logic_unsigned.all;

Entity MOD10counter is
Port( Clk: in std_logic;
SLoad: in std_logic;
Clr: in std_logic;
Q: out std_logic_vector(0 to 3));
End MOD10counter;

Architecture behavioural of MOD10counter is

signal temp: std_logic_vector(0 to 3);

begin
Process(Clk) is
Begin
If (Clk’event and clk=’1’) then
If Clr=’1’ then
Temp <= “0000”;
Elseif SLoad =’1’ then
Temp <= “1001”;
End if;
End if;
End if;
End process;