ONLINE CLASS (2020-21)

PROGRAMMING IN HDL(SEC1406)

MENTORS
Dr.T.RAVI
Dr.T.VINO
Dr.S.Karthikeyan
Mr.M.A.Muthiah
Department of ECE
Sathyabama Institute of Science and Technology
SYLLABUS
Course Outcome
After the completion of course student will be able to

CO1 Understand the requirements of VHDL design flow

CO2 Interpret the Verilog language elements and its relevance to
digital design
CO3 Apply the Modelling Styles for Simulation, Synthesis and
Test Bench Creation.
CO4 Analyse the Performance Study of Combinational and
Sequential logic design using Verilog
CO5 Evaluate State Machine and Memory designs by Verilog
CO6 Create and realize the system in FPGA using Verilog
UNIT 1- CONCEPTS IN VHDL
HDL – Hardware Description Language
Digital System Design Process

Requirements
• Design flows operate at
multiple levels of abstraction
Functional Design Behavioral Simulation
• Need a uniform description to
Register Transfer RTL Simulation
translate between levels
Level Design Validation
• Increasing costs of design and
Logic Simulation fabrication necessitate greater
Logic Design Verification
Fault Simulation
reliance on automation via CAD
tools
Timing Simulation
Circuit Design
Circuit Analysis – $5M - $100M to design
new chips
Design Rule Checking
– Increasing time to market
Physical Design

pressures
Description for Manufacture
HDL – Hardware Description Language
1. VHDL
2. Verilog HDL
VHDL
V H SIC Very High Speed Integrated Circuit
Hardware
Description
Language

VHDL
based on 5 languages 4 Different Styles of Description
•Net list Language 1. Structural Modelling
•Concurrent Language 2. Data flow Modelling
•Sequential Language 3. Behavioral Modelling
•Timing Specification 4. Mixed Modelling
•Waveform Generation
 VHDL
History of VHDL
1981 - DoD US for developing VHSIC
1983 - DoD - IBM, Texas Instruments, Intermetrics for standard of VHDL
1985 - Version 7.2 of VHDL
1986 - Applied for IEEE Standard
1987 - Standardized by IEEE - IEEE 1076-1987
1993 - Enhanced version of the language is defined -IEEE 1076-1993
Additional standardized packages provide definitions of data types and
expressions of timing data
– IEEE 1164 (data types)
– IEEE 1076.3 (numeric)
– IEEE 1076.4 (timing)
 VHDL
VHDL Capabilities
•Exchange medium between chip vendors and CAD tool users.
•Support Hierarchy
•Support Flexible design methodology
•Language not a technology specific
•Supports both synchronous and asynchronous timing models.
•Various delay constraints can be described.
•Allows defining new data types.
•IEEE and ANSI standard, therefore very portable.
•Supports a wide range of abstraction levels, design modelling styles.
•Language Publically available, Human readable, Machine readable
•Test benches are available in the same Language.
VHDL
Hardware Abstraction
VHDL
Primary Design Constructs
Five primary design constructs, also known as “Design Units” used to describe logic

Entity Declaration

– The Interface of a logic circuit.

Architecture Body

– Particular implementation of an entity

Configuration Declaration

– Binds entities, architectures, and component declarations

Package declaration

– Convenient way to define and group functions, procedures, types, components etc.

Package body

– Implementation of the functionality exposed by package declaration.

VHDL
ENTITY DECLARATION
External view of an entity is called Entity declaration, Defines
the interface of the hardware module to the outside
environment in which it is used.
Entity declaration syntax

entity entity_name is
port(port_list);
end entity_name;

Half Adder
entity half_adder is
port (a, b: in std_logic; sum, carry: out std_logic);
end half_adder;
VHDL
Full Adder

entity full_adder  is
port ( a,b,cin : in  std_logic; sum,cout : out  std_logic);
end full_adder;

2*4 Decoder

entity decoder  is
port ( a,b: in  std_logic; y: out  std_logic_vector(0 to 3));
end decoder;
VHDL
Multiplexer

entity multiplexer  is
port ( d: in std_logic_vector(0 to 3);a,b:in std_logic; y: out std_logic);
end multiplexer;

Code convertor

entity g2b  is
port ( g: in  std_logic_vector(0 to 3); b: inout  std_logic_vector(0 to 3));
end g2b;
VHDL
Architecture Body
Architecture body specifies internal view of an entity, internal view can be represented in 4
different styles of description, they are

1. Structural model

2. Data flow model

3. Behavioral model

4. Mixed Model

Architecture body syntax

architecture architecture_name of entity_name is
  architecture_declarations;
begin
  statements;
end architecture_name ;
VHDL
Architecture Body
1. Structural model

- Set of Interconnected components

2. Data flow model

- Set of Concurrent Assignment Statements

3. Behavioral model

- Set of Sequential Assignment Statements

4. Mixed Model

- Combination of any 2 or all.

VHDL
Structural Model
Architecture body of an entity described as Set of Interconnected components is called

Structural model.

There are tow parts in structural model

1.Component Declaration

- Declaring all formal parameters present in architecture body

2.Component Instantiation

- Interfacing of formal parameters with actual parameters

•Actual Parameters

The parameters which declared in entity declaration

•Formal Parameters

The parameters which declared in component declaration to describe the structure of component
VHDL - Structural Model
Half Adder
architecture HA_STR of half_adder is

component xor_gate

port(x,y : in std_logic; z : out std_logic);

end component;

component and_gate

port(p,q : in std_logic; r : out std_logic);

entity half_adder is
end component;
port (a, b: in std_logic; sum, carry: out std_logic);
begin
end half_adder;
L1 : xor_gate port map (a,b,sum);

L2 : and_gate port map (a,b,carry);

end HA_STR;
VHDL - Structural Model
Half Sutractor
architecture HS_STR of half_subtractor is
component xor_gate
port(x,y : in std_logic; z : out std_logic);
end component;
component and_gate
port(p,q : in std_logic; r : out std_logic);
end component;
component not_gate
port(m : in std_logic; n : out std_logic);
end component;
entity half_subtractor is
signal s1 : std_logic;
port (a, b: in std_logic; diff,bor: out std_logic);
begin
end half_subtractor;
L1 : xor_gate port map (a,b,diff);
L2 : not_gate port map (a,s1);
L3 : and_gate port map (s1,b,bor);
end HS_STR;
VHDL - Structural Model
Full Adder
architecture FA_STR of full_adder is
component xor_gate
port(x,y : in std_logic; z : out std_logic);
end component;
component and_gate
port(p,q : in std_logic; r : out std_logic);
end component;
component or_gate
port(m,n : in std_logic; o : out std_logic);
end component;
signal s1,s2,s3 : std_logic;
entity full_adder is
begin
port (a, b, cin: in std_logic; sum,carry: out std_logic);
L1 : xor_gate port map (a,b,s1);
L2 : xor_gate port map (s1,cin,sum); end full_adder;
L3 : and_gate port map (a,b,s2);
L3 : and_gate port map (s1,cin,s3);
L3 : or_gate port map (s3,s2,carry);
end FA_STR;
VHDL - Structural Model
Decoder
architecture DEC_STR of decoder is
component not_gate
port(m : in std_logic; n : out std_logic);
end component;
component and_gate
port(p,q : in std_logic; r : out std_logic);
end component;
signal s1,s2 : std_logic;
begin
L1 : not_gate port map (a,s1);
entity decoder  is
L2 : not_gate port map (b,s2);
port ( a,b: in  std_logic; y: out 
L3 : and_gate port map (s1,s2,y(0));
std_logic_vector(0 to 3));
L4 : and_gate port map (s1,b,y(1));
end decoder;
L5 : and_gate port map (a,s2,y(2));
L6 : and_gate port map (a,b,y(3));
end DEC_STR;
VHDL - Structural Model
Multiplexer
architecture MUX_STR of multiplexer is
component not_gate
port(m : in std_logic; n : out std_logic);
end component;
component and_gate
port(p,q,r : in std_logic; s : out std_logic);
end component;
component or_gate
port(e,f,g,h: in std_logic; i out std_logic);
end component;
signal s1,s2,s3,s4,s5,s6: std_logic;
begin entity multiplexer  is
L1 : not_gate port map (a,s1); port ( d: in std_logic_vector(0 to 3);
L2 : not_gate port map (b,s2); a,b:in std_logic; y: out std_logic);
L3 : and_gate port map (s1,s2,d(0),s3); end multiplexer;
L4 : and_gate port map (s1,b,d(1),s4);
L5 : and_gate port map (a,s2,d(2),s5);
L6 : and_gate port map (a,b,d(3),s6);
L7 : or_gate port map (s3,s4,s5,s6,y);
end MUX_STR;
VHDL
Dataflow Model
Architecture body of an entity described as Set of concurrent signal assignment

statements is called Dataflow model.

Concurrent mean parallel or simultaneous execution, i.e order of the statement is not important.

Architecture body syntax for Dataflow model

architecture architecture_name of entity_name is
  [signal_declarations;]
begin
  concurrent signal assignment statements;
end architecture_name ;

architecture HA-DF of half_adder is
begin entity half_adder is
  sum <= a xor b; port (a, b: in std_logic; sum, carry: out std_logic);
carry <= a and b;
end HA_DF; end half_adder;
VHDL - Dataflow Model
Half Sutractor
Architecture body of Half Subtractor using signal
architecture HS_DF of half_subtractor is
signal s1 : std_logic;
begin
s1 <= not a;
diff <= a xor b;
bor <= s1 and b;
end HS_DF;

entity half_subtractor is
Architecture body of Half Subtractor without using signal
port (a, b: in std_logic; diff, bor: out std_logic);
architecture HS_DF of half_subtractor is
end half_subtarctor;
begin
diff <= a xor b;
bor <= (not a) and b;
end HS_DF;
VHDL - Dataflow Model
Full Adder
Architecture body of Full Adder using signal
architecture FA_DF of full_adder is
signal s1,s2,s3 : std_logic;
begin
s1 <= a xor b;
sum <= s1 xor cin;
s2<= a and b;
s3<= s1 and cin;
carry <= s3 or s2;
end FA_DF;
entity full_adder is
Architecture body of Full Adder without using signal
port (a, b, cin: in std_logic; sum,carry: out std_logic);
architecture FA_DF of full_adder is
end full_adder;
begin
sum <= (a xor b) xor cin;
carry <= ((a xor b) and cin) or (a and b);
end FA_DF;
VHDL - Dataflow Model
Decoder
Architecture body of Decoder using signal
architecture DEC_DF of decoder is
signal s1,s2 : std_logic;
begin
s1 <= not a;
s2 <= not b;
d(0) <= s1 and s2;
d(1) <= s1 and b;
d(2) <= a and s2;
d(3) <= a and b;
end DEC_DF;

Architecture body of Decoder without using signal entity decoder is

architecture DEC_DF of decoder is port (a, b : in std_logic; d: out std_logic_vector(0 to
begin
3));
d(0) <= (not a) and (not b);
end decoder;
d(1) <= (not a) and b;
d(2) <= a and (not b);
d(3) <= a and b;
VHDL-Behavioral Model
The behavioral style of modeling specifies the behavior of an entity as a set of statements

hat are executed sequentially in the specified order.

This set of sequential statements, that are specified inside a process statement, do not

explicitly specify the structure of the entity but merely specifies its functionality.

A process statement is a statement that can appear within an architecture body

Architecture body syntax for Behavioral model

architecture architecture_name of entity_name is
begin
 process(sensitivity_list)
[variable_declarations;]
begin
Sequential assignment statements;
end process;
end architecture_name ;
VHDL - Behavioral Model
Decoder
entity decoder  is
port (a,b: in std_logic; d: out std_logic_vector(0 to 3));
end decoder;

Architecture body of Decoder using Dataflow model Architecture body of Decoder using Behavioral model
architecture DEC_DF of decoder is architecture DEC_BEH of decoder is
signal s1,s2: std_logic; begin
begin process (a,b)
s1 <= not a; variable s1,s2 : std_logic;
s2 <= not b; begin
d(0) <= s1 and s2; s1 := not a;
d(1) <= s1 and b; s2 := not b;
d(2) <= a and s2; d(0) <= s1 and s2;
d(3) <= a and b; d(1) <= s1 and b;
end DEC_DF; d(2) <= a and s2;
d(3) <= a and b;
end process;
end DEC_BEH;
 VHDL - Behavioral Model
Full Adder
entity full_adder is
port (a, b, cin: in std_logic; sum,carry: out std_logic);
end full_adder;

architecture FA_BEH of full_adder is

architecture FA_DF of full_adder is
begin
signal s1,s2,s3 : std_logic;
process(a,b,cin)
begin
variable s1,s2,s3 : std_logic;
s1 <= a xor b;
begin
s2<= a and b;
s1 := a xor b;
s3<= s1 and cin;
s2 := a and b;
sum <= s1 xor cin;
s3 := s1 and cin;
carry <= s3 or s2;
sum <= s1 xor cin;
end FA_DF;
carry <= s3 or s2;
end process;
end FA_BEH;

architecture FA_BEH of full_adder is

architecture FA_DF of full_adder is
begin
begin
process(a,b,cin)
sum <= (a xor b) xor cin;
begin
carry <= ((a xor b) and cin) or (a and b);
sum <= (a xor b) xor cin;
end FA_DF;
carry <= ((a xor b) and cin) or (a and b);
end process;
end FA_BEH;
VHDL - Behavioral Model
Multiplexer
entity multiplexer  is
port ( d: in  std_logic_vector(0 to 3); a,b: in std_logic; y: out  std_logic);
end multiplexer;

architecture MUX_DF of multiplexer is architecture MUX_BEH of multiplexer is

signal s1,s2,s3,s4,s5,s6 : std_logic; begin
begin process (a,b,d)
s1 <= not a; variable s1,s2,s3,s4,s5,s6 : std_logic;
s2 <= not b; begin
s3 <= s1 and s2 and d(0); s1 := not a;
s4 <= s1 and b and d(1); s2 := not b;
s5 <= a and s2 and d(2); s3 := s1 and s2 and d(0);
s6 <= a and b and d(3); s4 := s1 and b and d(1);
y <= s3 or s4 or s5 or s6; s5 := a and s2 and d(2);
end MUX_DF; s6 := a and b and d(3);
y <= s3 or s4 or s5 or s6;
end process;
 VHDL - Multiplexer
architecture MUX_STR of multiplexer is
entity multiplexer  is
component not_gate
port ( d: in  std_logic_vector(0 to 3);
port(m : in std_logic; n : out std_logic);
a,b: in std_logic; y: out  std_logic);
end component;
end multiplexer;
component and_gate
port(p,q,r : in std_logic; s : out std_logic);
end component; architecture MUX_BEH of multiplexer is
component or_gate architecture MUX_DF of multiplexer is begin
port(e,f,g,h: in std_logic; i out std_logic); signal s1,s2,s3,s4,s5,s6 : std_logic; process (a,b,d)
end component; begin variable s1,s2,s3,s4,s5,s6 : std_logic;
signal s1,s2,s3,s4,s5,s6: std_logic; s1 <= not a; begin
begin s2 <= not b; s1 := not a;
L1 : not_gate port map (a,s1); s3 <= s1 and s2 and d(0); s2 := not b;
L2 : not_gate port map (b,s2); s4 <= s1 and b and d(1); s3 := s1 and s2 and d(0);
L3 : and_gate port map (s1,s2,d(0),s3); s5 <= a and s2 and d(2); s4 := s1 and b and d(1);
L4 : and_gate port map (s1,b,d(1),s4); s6 <= a and b and d(3); s5 := a and s2 and d(2);
L5 : and_gate port map (a,s2,d(2),s5); y <= s3 or s4 or s5 or s6; s6 := a and b and d(3);
L6 : and_gate port map (a,b,d(3),s6); end MUX_DF; y <= s3 or s4 or s5 or s6;
L7 : or_gate port map (s3,s4,s5,s6,y); end process;
end MUX_STR; end MUX_BEH;
 VHDL - Mixed Model - Full Adder
architecture FA_MIX of full_adder is
component xor_gate
port(x,y : in std_logic; z : out std_logic);
end component;
component and_gate
port(p,q : in std_logic; r : out std_logic);
end component;
signal s1,s2,s3 : std_logic;
begin
L1 : xor_gate port map (a,b,s1);
L2 : and_gate port map (a,b,s2); entity full_adder is

sum <= s1 xor cin; port (a, b, cin: in std_logic; sum,carry: out std_logic);

s3 <= s1 and cin; end full_adder;

process(a,b,cin)
variable s2,s3 : std_logic;
begin
carry <= s3 or s2;
end process;
end FA_MIX;
 VHDL - Mixed Model - Multiplexer
architecture MUX_MIX of multiplexer is
component not_gate
port(m : in std_logic; n : out std_logic);
end component;
signal s1,s2,s3,s4,s5,s6 : std_logic;
begin
L1 : not_gate port map (a,s1);
L2 : not_gate port map (b,s2);
s3 <= s1 and s2 and d(0);
s4 <= s1 and b and d(1); entity multiplexer  is
s5 <= a and s2 and d(2); port ( d: in  std_logic_vector(0 to 3); a,b: in std_logic;
s6 <= a and b and d(3); y: out  std_logic);
process(a,b,d) end multiplexer;
variable s3,s4,s5,s6 : std_logic;
begin
y <= s3 or s4 or s5 or s6;
end process;
end MUX_MIX;
VHDL – Basic Language Elements

Basic Language Elements of VHDL are

•Identifiers
•Comments
•Data Objects
•Data Types
•Operators
VHDL – Basic Language Elements
Identifiers
- Identifiers are used to name items in a VHDL model.
Basic identifier: composed of a sequence of one or more characters
A basic identifier may contain only capital ‘A’ - ’Z’ , ‘a’ - ’z’, ‘0’ - ’9’,
underscore character ‘_’
• first character must be a letter, last character must NOT be an
underscore
• Two underscores cannot occur concurrently
• case insensitive: COUNT, count, Count, counT are all the same
• Keywords can not be used as basic identifiers

Extended identifier: sequence of characters written between two backslashes

Any printable characters can be used including %, $, *, etc.
• lower case and upper case are distinct
• examples: /2FOR$/ , /countNow!/ , /&#$(@#&!!!/
 VHDL – Basic Language Elements
Comments
•Its non executable or readable parameter for understanding purpose.
•The comments to be proceeded by two consecutive hyphens(--)
Example
entity half_adder is
port (a, b: in std_logic; sum, carry: out std_logic);
end half_adder; -- end of entity with entity name
architecture HA-DF of half_adder is
begin
  sum <= a xor b; -- a xor with b, result assigned to sum
carry <= a and b; -- a and with b, result assigned to carry
end HA_DF; -- end of architecture with architecture name
 VHDL – Basic Language Elements
Data Objects
– hold a value of a specified type
constant: holds a single value of a specified type and cannot be changed
throughout the simulation
– constant declaration:
• constant RESULT: BIT:=1;
• constant FALL_TIME: TIME:=10ns
variable: holds a single value of a specified type but can be changed
throughout the simulation
• variable ABAR:BIT;
• variable STATUS:BIT_VECTOR(3 downto 0);
signal: holds a list of values including current value and a list of possible
future values
• typically used to model wires and flip-flops
• signal DATA_BUS:BIT_VECTOR(0 to 31)
file: same as with any computer file, contains data
 VHDL – Basic Language Elements
Data Types
– Is a name which is associated with a set of values and a set of operations.
Major Data Types:
Scalar Type
Composite Type
Access Type
File Type

There can also be user-defined types and subtypes

A subtype is a type with a (possibly) added constraint

syntax: subtype subtype_name is base_type range range_constraint;
example: subtype DIGITS is integer range 0 to 9;
 VHDL – Basic Language Elements
Data Types
Scalar types
Enumeration – defines a type that has a set of user-defined values
type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’,’-’);
‘u’ unspecified, ‘x’ unknown, ‘0’ strong zero, ‘1’ strong one
‘z’ high impedance, ‘w’ weak unknown, ‘l’ weak zero, ‘h’ weak one, ‘-’ don’t
care
Integer – values fall within the specified integer range
type REG_SIZE is range 0 to 31
subtype WORD is REG_SIZE range 0 to 15
Floating Point –real decimal types
Physical – represent measurement of some physical quantity like
time, voltage, or current
 VHDL – Basic Language Elements
Composite Types
– a collection of values
Array Types – collection of values all belonging to a single type
• BIT_VECTOR and STRING are pre-defined one-dimensional array
types
type DATA_BYTE is array (0 to 7) of BIT;
type MEMORY is array (0 to 127) of DATA_BYTE;
Record Types – collection of values that may belong to different types
type MODULE is
record
SUM : BIT_VECTOR(0 to 7);
COUT : BIT;
end record;
 VHDL – Basic Language Elements
Access Type
Values belonging to an access type are pointers to a allocated object of
some other type.
Example :
type PTR is access MODULE;

File Type
Objects of file type represent files in the host environment.
Syntax :
type file_type_name is file of type_name;
VHDL – Basic Language Elements
Operators
logical operators
• and, or, nand, nor, xor, xnor, not
relational operators
• <, >, =, <=, >=, /= -- /= means not equal to
shift operators
• sll, srl, sla, sra, rol, ror
adding operators
• +, -, & -- & is concatenation
multiplying operators
• *, /, mod, rem
miscellaneous operators
• abs, ** -- ** is exponentiation
 VHDL – Structural Model
• An entity is modeled as a set of components connected by signals, that
is,
as a net-list.
• The behavior of the entity is not explicitly apparent from its model.
•The component instantiation statement is the primary mechanism used for
describing such a model of an entity.
• COMPONENT & PORT MAP statements are used to implement structural
modeling.
• The component instantiation statements are concurrent statements, and
their order of appearance in the architecture body is therefore not important.
• A component can be instantiated any number of times.
• Each instantiation must have a unique component label
VHDL – Structural Model – Component Declaration
A component in a structural description must first be declared using a component declaration.
A component declaration declares the name and the interface of a component (similar to the
entity).
The interface specifies the mode and the type of ports.

The syntax of a simple form of component declaration is:

COMPONENT Component-Name [IS]
PORT(List-of-Interface-Ports);
END COMPONENT [Component-Name ];

The component-name may or may not refer to the name of an entity already existing in a
library. If it does not, it must be explicitly bound to an entity.
The binding information can be specified using a configuration.
The List-Of-Interface-Ports specifies the name, mode, and type for each port of the
component in a manner similar to that specified in an entity declaration.
The names of the ports may also be different from the names of the ports in the entity to which
it may be bound (different port names can be mapped in a configuration)
 VHDL-Structural Model-Component Instantiation
A component instantiation statement defines a association of formal and actual parameters. It
associates the signals in the entity with the ports of that component.

A format of a component instantiation statement:

Component-Label: Component-Name PORT MAP (association-list);

The Component-Label can be any legal identifier and can be considered as the name of the
instance.
The Component-Name must be the name of a component declared earlier using a component
declaration.
The association-list, associates signals in the entity, called actuals, with the ports of a component,
called formals.
There are two ways to perform the association of formals with actuals:
1. Positional association
2. Named association
 VHDL-Structural Model- Component Instantiation

In positional association, each actual in the component instantiation is mapped by

position with each port in the component declaration. That is, the first port in the
component declaration corresponds to the first actual in the component instantiation,
the second with the second, and so on.

If a port in a component instantiation is not connected to any signal, the keyword

OPEN can be used to signify that the port is not connected.
For example
d1 : dff PORT MAP (data, ck, s1, open);
In named association, an association-list is of the form:
formal1 => actual1 ,formal2=> actual2, ... formaln=> actualn
For example
d1 : dff PORT MAP (d => data, clk => ck, q => s1, qb => s2);
In named association, the ordering of the associations is not important since the
mapping between the actuals and formals is explicitly specified.
 VHDL – Dataflow Model
The Data-Flow modeling is a collections of concurrent statements.
All the statements must be write only in the architecture body.
There is no meaning to the order of the statements.
There are 3 Data-Flow statement:
– Concurrent Signal Assignment entity decoder is
– Conditional Signal Assignment port (a, b : in std_logic;
– Selected Signal Assignment d: out std_logic_vector(0 to 3));
end decoder;
architecture DEC_DF of decoder is
Concurrent Signal Assignment signal s1,s2 : std_logic;
The syntax is: begin
target-signal _1<= expression_1; s1 <= not a;
target-signal _2<= expression_2; s2 <= not b;
d(0) <= s1 and s2;
–Examples:
d(1) <= s1 and b;
z <= a; d(2) <= a and s2;
z <= (a and b) after 20 ns; d(3) <= a and b;
z <= a after 10 ns, ‘1’ after 20 ns, ‘0’ after 30 ns; end DEC_DF;
VHDL – Dataflow Model
Conditional Signal Assignment Statement
•Also called a When-Else Statement.
•Concurrent statement, thus all signals.
entity decoder is
•Similar to a sequential IF-THEN-ELSE statement.
•Select one of several values to drive an output port (a, b : in std_logic;
signal. d: out std_logic_vector(0 to 3));
•Selection based on first condition that is TRUE.
end decoder;
Syntax:
target_signal <= value1 when condition1 else architecture DEC_CS of decoder is
value2 when condition2 else
begin
... d <= “0001” when (a = ‘0’ and b = ‘0’) else
value9;
“0010” when (a = ‘0’ and b = ‘1’) else
“0100” when (a = ‘1’ and b = ‘0’) else
“1000”;
end DEC_CS;
VHDL – Dataflow Model
Selected Signal Assignment Statement
•Also called a With-Select-When statement.
•Concurrent statement, thus all signals.
•Similar to a sequential CASE statement.
entity decoder is
•Select one of several values to drive an output
signal. port (a : in std_logic_vector (0 to 1);
•Selection based on all possible values of a selector
d: out std_logic_vector(0 to 3));
expression.
Syntax:
with expression select end decoder;
target_signal <= value1 when condition1,
value2 when condition2, architecture DEC_SS of decoder is
... begin
value9 when condition9;
with a select
d <= “0001” when “00” ,
“0010” when “01” ,
“0100” when “10” ,
“1000” when “11”;
end DEC_SS;
VHDL – Behavioral Model
The process statement contains sequential statements that describe the functionality
of an entity in sequential terms
The sensitivity list is a set of signals which willSome
cause thesequential
of the process tostatements
execute in
in Behavioral
sequential order when an event occurs. model are

1.Variable Assignment Statement

Syntax 2.Signal Assignment Statement
3.Wait Statement ( wait on, wait until, wait for )
4.If Statement (conditional)
architecture architecture_name of entity_name is 5.Case Statement (Selection)
begin 6.Loop Statement (for loop, while loop, no loop)
 process(sensitivity_list) 7.Null Statement (No operation)
8.Exit Statement (Exit from the loop)
[variable_declarations;]
9.Next statement (Exit from one loop, and execute next
begin loop)
Sequential assignment statements; 10.Assertion Statement (Modelling constrain)
end process; 11.Report Statement (Display Message)
end architecture_name ; 12.Procedure call Statement (Linkage)
13.Return Statement
VHDL – Behavioral Model
If statement entity decoder is
port (a, b : in std_logic; d: out
– selects statements for execution based
std_logic_vector(0 to 3));
upon a condition
end decoder;
Syntax
architecture DEC_IF of decoder is
if condition_1 then
sequential_statement_1; begin
elsif condition_2 then process (a,b)
sequential_statement_2; begin
: if (a = ‘0’ and b = ‘0’) then
: d <= “0001”;
else sequential_statement_n;
elsif (a = ‘0’ and b = ‘1’) then
end if;
d <= “0010”;
elsif (a = ‘1’ and b = ‘0’) then
d <= “0100”;
else d<= “1000”;
end if;
end process;
end DEC_IF;
VHDL – Behavioral Model
Case statement
– selects
one branch of execution from a list of entity decoder is
many based upon selected expression port (a : in std_logic_vector(0 to 1); d:
out std_logic_vector(0 to 3));
Syntax: end decoder;
case expression is architecture DEC_CASE of decoder is
when choice_1 => statement_1;
begin
when choice_2 => statement_2;
: process (a)
when choice_n => statement_n; begin
end case; case a is
when “00” => d <= “0001”;
when “01” => d <= “0010”;
when “10” => d <= “0100”;
when “11” => d <= “1000”;
end case;
end process;
end DEC_CASE;
 VHDL - Decoder
entity decoder  is
port ( a,b: in  std_logic,
d: out std_logic_vector(0 to 3));
end decoder; entity decoder  is
architecture DEC_STR of decoder is port ( a,b: in  std_logic,
component not_gate d: out std_logic_vector(0 to 3));
port(m : in std_logic; n : out std_logic); entity decoder  is
end decoder;
end component; port ( a,b: in  std_logic,
architecture DEC_BEH of decoder is
component and_gate d: out std_logic_vector(0 to 3));
begin
port(p,q: in std_logic; r : out std_logic); end decoder;
process (a,b)
end component; architecture DEC_DF of decoder is
variable s1,s2 : std_logic;
signal s1,s2 : std_logic; signal s1,s2 : std_logic;
begin
begin begin
s1 := not a;
L1 : not_gate port map (a,s1); s1 <= not a;
s2 := not b;
L2 : not_gate port map (b,s2); s2 <= not b;
d(0) <= s1 and s2;
L3 : and_gate port map (s1,s2,d(0)); d(0) <= s1 and s2;
d(1) <= s1 and b;
L4 : and_gate port map (s1,b,d(1)); d(1) <= s1 and b;
d(2) <= a and s2;
L5 : and_gate port map (a,s2,d(2)); d(2) <= a and s2;
d(3) <= a and b;
L6 : and_gate port map (a,b,d(3)); d(3) <= a and b;
end process;
end DEC_STR; end DEC_DF;
end MUX_BEH;
VHDL - Decoder
entity decoder  is
port ( a,b: in  std_logic,
d: out std_logic_vector(0 to 3));
end decoder;
architecture DEC_MIX of decoder is
component not_gate
port(m : in std_logic; n : out std_logic);
entity decoder is
end component; entity decoder is
port (a, b : in std_logic;
signal s1,s2 : std_logic; port (a : in std_logic_vector (0 to 1);
d: out std_logic_vector(0 to 3));
begin d: out std_logic_vector(0 to 3));
end decoder;
L1 : not_gate port map (a,s1); end decoder;
architecture DEC_CS of decoder is
L2 : not_gate port map (b,s2); architecture DEC_SS of decoder is
begin
d(0) <= s1 and s2; begin
d <= “0001” when (a = ‘0’ and b = ‘0’)
d(1) <= s1 and b; with a select
else
process (a,b) d <= “0001” when “00” ,
“0010” when (a = ‘0’ and b = ‘1’)
variable s1,s2 : std_logic; “0010” when “01” ,
else
begin “0100” when “10” ,
“0100” when (a = ‘1’ and b = ‘0’)
d(2) <= a and s2; “1000” when “11”;
else
d(3) <= a and b; end DEC_SS;
“1000”;
end process;
end DEC_CS;
 VHDL - Decoder
entity decoder is
port (a, b : in std_logic; d: out
entity decoder is
std_logic_vector(0 to 3));
port (a : in std_logic_vector(0 to 1); d:
end decoder;
out std_logic_vector(0 to 3));
architecture DEC_IF of decoder is
end decoder;
begin
architecture DEC_CASE of decoder is
process (a,b)
begin
begin
process (a)
if (a = ‘0’ and b = ‘0’) then
begin
d <= “0001”;
case a is
elsif (a = ‘0’ and b = ‘1’) then
when “00” => d <= “0001”;
d <= “0010”;
when “01” => d <= “0010”;
elsif (a = ‘1’ and b = ‘0’) then
when “10” => d <= “0100”;
d <= “0100”;
when “11” => d <= “1000”;
else d<= “1000”;
end case;
end if;
end process;
end process;
end DEC_CASE;
end DEC_IF;
 VHDL – Model Quiz
1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals

2. Which of the following can be the name of an entity?

a) NAND
b) Nand_gate
c) Nand gate
d) AND

B
VHDL – Model Quiz
3. Which of the following is correct syntax for entity declaration?
a)
ENTITY entity_name IS
PORT( signal_names : signal_modes signal_type;
signal_names : signal_modes signal_type);
END entity_name;
b)
ENTITY entity_name
PORT( signal_names : signal_modes;
signal_names : signal_modes);
END ENTITY;
c)
ENTITY entity_name IS
PORT port_name
( signal_names : signal_modes signal_type;
signal_names : signal_modes signal_type);
END entity_name;
d)
ENTITY entity_name
PORT port_name
(signal_names : signal_modes;
A
signal_names : signal_modes);
END ENTITY;
VHDL – Model Quiz
4. Refer to the VHDL code given below, how many input-output pins are there in MUX entity?
ENTITY mux IS
Port ( a,b : IN STD_LOGIC; d : IN STD_LOGIC_VECTOR(0 to 3); Y : OUT STD_LOGIC);
END mux;
a)5
b)7 B
c)6
d)4

5. The entity name ‘xyz’ and ‘XYZ’ will be treated the same.
a)True
b) False
A
6. Which of the following mode of the signal is bidirectional?
a) IN
b) OUT
c) INOUT
d) BUFFER C
7. Which of the following is the correct syntax for architecture declaration and definition?

a) ARCHITECTURE architecture_type OF entity_name IS

Declarations_for_architecture;
BEGIN
Code; ….
END architecture_name;

b) ARCHITECTURE architecture_name OF entity_name IS

BEGIN
Declarations_for_architecture;
Code; ….
END architecture_name;

c) ARCHITECTURE architecture_type OF entity_name IS

BEGIN
Declarations_for_architecture;
Code; ….
END architecture_type;

d) ARCHITECTURE architecture_name OF entity_name IS

Declarations_for_architecture;
BEGIN
Code; …. D
END architecture_name;
8. The statements in between the keyword BEGIN and END are called _______
a) Concurrent statements
b) Netlist
c) Declaration statement
A
d) Entity function

9. Which of the following is the correct architecture for a simple Nand gate?
a) ARCHITECTURE my_arch OF nand_gate IS
BEGIN
x <= a NAND b;
END my_arch;

b) BEGIN
ARCHITECTURE my_arch OF nand_gate IS
x <= a NAND b;
END behavioral;

c) BEGIN
ARCHITECTURE behavioral OF nand_gate IS
x <= a NAND b;
END my_arch;

d) ARCHITECTURE nand OF nand_gate IS

BEGIN
x <= a NAND b; A
END nand;