Following is the VHDL code for an unsigned 8-bit greater or equal comparator.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compar is
  port(A,B : in std_logic_vector(7 downto 0);
      CMP : out std_logic);
end compar;
architecture archi of compar is
  begin
    CMP <= '1' when A >= B
            else '0';
end archi;