Q35. Design Parallel/serial load shift register with enable input.

Shifting
operation: s_l=0. Parallel load: s_l=1. Provide the VHDL code and create a
VHDL testbench. The clock frequency must be 50 MHz. Submit the
implementaion of your design in google doc.

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sipo is
port( res: in std_logic;
s_1: in std_logic;
clk: in std_logic;
pout: out std_logic_vector(3 downto 0));
end sipo;

architecture beh of sipo is

signal temp: std_logic_vector( 3 downto 0);
begin
process( clk, res)
begin
if(res='1') then
temp<="0000";
elsif (clk'event and clk ='1') then
temp(3)<=s_1;
temp(2)<=temp(3);
temp(1)<=temp(2);
temp(0)<=temp(1);
end if;
end process;
pout<=temp;
end beh;
Test Bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sipotb is
-- Port ( );
end sipotb;

architecture Behavioral of sipotb is

COMPONENT sipo
PORT(
res : IN std_logic;
s_1 : IN std_logic;
clk : IN std_logic;
pout : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

signal res : std_logic := '0';

signal s_1 : std_logic := '0';
signal clk : std_logic := '0';
signal pout : std_logic_vector(3 downto 0);
constant clk_period : time := 20 ns;

begin

uut: sipo port map (

res => res,
s_1 => s_1,
clk => clk,
pout => pout
);

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
 clk <= '1';
wait for clk_period/2;
end process;

stim_proc: process
begin
s_1<='0';
wait for 20 ns;
s_1<='0';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='0';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='0';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='0';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
s_1<='0';
wait for 20 ns;
s_1<='1';
wait for 20 ns;
wait;
wait;
end process;
END;

Schematic Diagram:
Output Waveform: