NAME: SHRESHT GUPTA

BRANCH: ECE-II
ROLL NO.: 20211502818
BATCH: P1

EXPERIMENT 8

AIM: Write a VHDL program for the following circuits, check the wave forms and hardware
generated.
a) ALU
b) Shift Register

SOFTWARE USED: ModelSim PE

MODELING STYLE USED: Behavioral style of modeling

THEORY:

ALU:

An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic
and logic operations on the operands in computer instruction words. In some processors, the ALU is
divided into two units, an arithmetic unit (AU) and a logic unit (LU).

The logic and arithmetic operations being implemented in the ALU are as follows:
1. Arithmetic Addition
ALU_Out = A + B;
2. Arithmetic Subtraction
ALU_Out = A – B;
3. Arithmetic Multiplication
ALU_Out = A * B;
4. Arithmetic Division
ALU_Out = A / B;
5. Logical Shift Left
ALU_Out = A logical shifted left by 1;
6. Logical Shift Right
ALU_Out = A logical shifted right by 1;
7. Rotate Left
ALU_Out = A rotated left by 1;
8. Rotate Right
ALU_Out = A rotated right by 1;
9. Logical AND
ALU_Out = A AND B;
10. Logical OR
ALU_Out = A OR B;
11. Logical XOR
ALU_Out = A XOR B;
12. Logical NOR
ALU_Out = A NOR B;
13. Logical NAND
ALU_Out = A NAND B;
14. Logical XNOR
ALU_Out = A XNOR B;
15. Greater comparison
ALU_Out = 1 if A > B else 0;
16. Equal comparison
ALU_Out = 1 A = B else 0;

SERIAL IN SERIAL OUT RIGHT SHIFT REGISTER:

A register capable of shifting binary information either to the right or the left is called a shift register.
SISO register accepts data serially i.e. one bit at a time on a single input line. It produced the stored
information on its single output also in serial form. Data shifted to right i.e. from high to low order bits
using shift-right register. A shift right register can also be built using D flip flop.
SERIAL IN AND PARALLEL OUT RIGHT SHIFT REGISTER:

SIPO register consists of one serial input & outputs are taken from all the flip-flops parallel. In this
register, data is shifted in serially but shifted out in parallel way. In order to shift the data out in
parallel, it is necessary to have all the data available at the outputs at the same time. Once the data is
stored, each bit appears on its respective output line & all the bits are available simultaneously, rather
than on a bit by bit basis as with the serial output.

CODE:

FOR ALU:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity alu is
port(a,b: in std_logic_vector(7 downto 0);
alu_sel: in std_logic_vector(3 downto 0);
alu_out: out std_logic_vector(7 downto 0);
carryout: out std_logic);
end alu;

architecture alu_ar of alu is

signal temp: std_logic_vector(8 downto 0) := "000000000";
begin
p1: process(a,b,alu_sel)
begin
case(alu_sel) is
when "0000" =>
alu_out <= a + b;
when "0001" =>
alu_out <= a - b;
when "0010" =>
alu_out <= std_logic_vector(to_unsigned((to_integer(unsigned(a))*to_integer(unsigned(b))),8));
when "0011" =>
alu_out <= std_logic_vector(to_unsigned((to_integer(unsigned(a))/to_integer(unsigned(b))),8));
when "0100" =>
alu_out <= a(6 downto 0) & '0';
when "0101" =>
alu_out <= '0' & a(7 downto 1);
when "0110" =>
alu_out <= a(6 downto 0) & a(7);
when "0111" =>
alu_out <= a(0) & a(7 downto 1);
when "1000" =>
alu_out <= a and b;
when "1001" =>
alu_out <= a or b;
when "1010" =>
alu_out <= a xor b;
when "1011" =>
alu_out <= a nor b;
when "1100" =>
alu_out <= a nand b;
when "1101" =>
alu_out <= a xnor b;
when "1110" =>
if(a > b) then
alu_out <= x"01";
else
alu_out <= x"00";
end if;
when "1111" =>
if(a = b) then
alu_out <= x"01";
else
alu_out <= "0";
end if;
when others =>
alu_out <= a + b;
end case;
end process;
temp <= ('0' & a) + ('0' & b);
carryout <= temp(8);
end architecture;
FOR ALU WITH TEST BENCH:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity alu_tb is
end alu_tb;

architecture alu_ar_tb of alu_tb is

component alu is
port(a,b: in std_logic_vector(7 downto 0);
alu_sel: in std_logic_vector(3 downto 0);
alu_out: out std_logic_vector(7 downto 0);
carryout: out std_logic);
end component;
signal a: std_logic_vector(7 downto 0) := "10110001";
signal b: std_logic_vector(7 downto 0) := "01001011";
signal alu_sel: std_logic_vector(3 downto 0) := "0101";
signal alu_out: std_logic_vector(7 downto 0);
signal carryout: std_logic;
begin
p1: alu port map(a => a,b => b,alu_sel => alu_sel,alu_out => alu_out,carryout => carryout);
end architecture;

FOR D FLIP FLOP:

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port(clk,din,rst:in std_logic;
dout:out std_logic);
end dff;

architecture d_arch of dff is

begin
process(rst,clk,din)
begin
if(rst='1') then
dout <= '0';
elsif(clk = '1' and clk'event) then
dout <= din;
end if;
end process;
end d_arch;

FOR SISO RIGHT SHIFT:

library ieee;
use ieee.std_logic_1164.all;

entity siso is
port(clk,din,rst:in std_logic;
dout:out std_logic);
end siso;

architecture siso1 of siso is

component dff is
port(clk,din,rst:in std_logic;
dout:out std_logic);
end component;
signal s: std_logic_vector(2 downto 0);
begin
u1: dff port map(clk=>clk,din=>din,rst=>rst,dout=>s(0));
u2: dff port map(clk=>clk,din=>s(0),rst=>rst,dout=>s(1));
u3: dff port map(clk=>clk,din=>s(1),rst=>rst,dout=>s(2));
u4: dff port map(clk=>clk,din=>s(2),rst=>rst,dout=>dout);
end architecture;

FOR SISO RIGHT SHIFT WITH TEST BENCH:

library ieee;
use ieee.std_logic_1164.all;

entity siso_tb is
end siso_tb;

architecture siso1_tn of siso_tb is

component siso is
port(clk,din,rst:in std_logic;
dout:out std_logic);
end component;
signal clk: std_logic := '0';
signal din: std_logic := '0';
signal rst: std_logic := '0';
signal dout: std_logic;
begin
p1: siso port map(clk => clk,din => din,rst => rst,dout => dout);
clk <= not clk after 20ns;
end architecture;

FOR SIPO RIGHT SHIFT:

library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(clk,din,rst:in std_logic;
dout:out std_logic_vector(2 downto 0));
end sipo;

architecture sipo1 of sipo is

component dff is
port(clk,din,rst:in std_logic;
dout:out std_logic);
end component;
signal s: std_logic_vector(2 downto 0);
begin
u1: dff port map(clk=>clk,din=>din,rst=>rst,dout=>s(0));
u2: dff port map(clk=>clk,din=>s(0),rst=>rst,dout=>s(1));
u3: dff port map(clk=>clk,din=>s(1),rst=>rst,dout=>s(2));
dout <= s;
end architecture;

FOR SIPO RIGHT SHIFT WITH TEST BENCH:

library ieee;
use ieee.std_logic_1164.all;

entity sipo_tb is
end sipo_tb;

architecture sipo1_tb of sipo_tb is

component sipo is
port(clk,din,rst:in std_logic;
dout:out std_logic_vector(2 downto 0));
end component;
signal clk: std_logic := '0';
signal din: std_logic := '1';
signal rst: std_logic := '0';
signal dout: std_logic_vector(2 downto 0);
begin
p1: sipo port map(clk => clk,din => din,rst => rst,dout => dout);
clk <= not clk after 20ns;
end architecture
WAVEFORM:

FOR ALU:

FOR SISO RIGHT SHIFT:

FOR SIPO RIGHT SHIFT:

RESULT:
We have implemented alu, serial in serial out right shift register and serial in parallel out right
shift register with test benches on VHDL simulator and observed its waveform.