UNIT V

VHDL
Very High speed integrated
circuit Hardware Descriptive
Language
By
Dr B MEENAKSHI
Professor/ EEE Dept.,
Sri SAIRAM ENGINEERING COLLEGE
 VHDL MODULE
[Case sensitive]

• Entity
• Architecture
 Entity
• Declares input and output signals
• Used to Give name (or) identifier by the user
• In the given eg: ‘half_adder’ is entity name or identifier
Identifier:
-> Should start with alphabet.
-> Can include special characters.
-> Case sensitive
Eg:
entity half-adder is
port (I1: in bit; I2: in bit;
sum_h: out bit; carry_out: out bit);
end half_adder;
 Entity continuation
• Ports may be either in or out
• Type bit specifies that ‘in’ or ‘out’ may take
the value either ‘0’ or ‘1’.
• ‘;’ conveys the ‘end of statement’
• ‘<┘’ or carriage return does not convey any
meaning.
• More than one architecture may be bound in
one ‘entity’
 Architecture
• Predefined word ‘architecture’ followed by user selected name followed by entity name.
in the given eg: implementation-> arch name;
• -- followed by comment
Eg:
entity example_1 is
port (I1,I2: in bit;
O1,O2: out bit);
end example_1;
architecture implementation_of_example_1 is
begin
O1<= I1 XOR I2; -- statement 1
O2<= I1 AND I2; -- statement 2
end implementation_of_example_1;
 VHDL Ports
• in-> input port; should appear at left side.
• out-> output port; should appear at left side.
• buffer-> both input or output port; can appear
at right or left side.
• inout-> can be used as both input and output
port.
• Linkage-> same as inout;
 operators
• Logical: AND, OR, NAND, NOR, XOR, XNOR,
NOT.
• Relational: =, /=,<,>,<=,>=
• Arithmetic: +,-,*,/,mod, rem, abs, &, **
[mod-modulus; rem- reminder; abs-absolute;
&-concatenation; **-exponent;]
• Shift and rotate operators: sll, srl, sla, sra, rol,
ror.
 Shift and rotate operators
• sll-> shift left logical, srl-> shift right logical, sla-> shift left
arithmetic, sra-> shift right arithmetic, rol-> rotate left, ror-
>rotate right.
Eg:
1.A sll 1-> shift A one position left logical; if A=1110 then after
shifting 110X
2. A sll 2-> shift A two position left logical; if A=1110 then after
shifting 10XX
3. A rol 1-> rotate A left ; if A=1110 then after rotating 1101
4. A ror 1-> rotate A right ; if A=1110 then after rotating 0111
 Data types
• Scalar: Bit, Boolean, integer, real, character, physical,
user_defined, severity
• Composite: bit_vector, Array, record
• Access: file
• Others: std_logic, std_logic_vector, signal, unsigned.
 Types of VHDL coding
• Data flow description: covers data types, designing
simple combinational circuits like adders, MUXes.
• Behavioural description: If statement, case st, loop
st; Design of sequential circuits such as counters
and flipflops.
• Structural description: gate level and register
transfer level
• Switch level description: transistor level
description
Simple Example
 Half adder- data flow description
entity halfadder is
port( a,b: in bits;
s,c: out bit);
end halfadder;
architecture HA_dtflw of halfadder is
begin
s<= a XOR b; -- to calculate sum
c<= a AND b; -- to calculate carry
end HA_dtflw;
 Half adder – behavioural model
• Include ‘process’ statement
entity halfadder is
port( a,b: in bits;
s,c: out bit);
end halfadder;
architecture HA_behav of halfadder is
begin
process(a,b)
begin
s<= a XOR b; -- to calculate sum
c<= a AND b; -- to calculate carry
end process;
end HA_behav;
 Half adder- structural description
• In half adder there are 2 components:
i. XOR gate ii. AND gate
• Both components described separately and
then used inside the system.
• While using components, the library
statements are to be included.
 Half adder- structural description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
port( a,b: in std_logic;
s,c: out std_logic);
end halfadder;

Architecture continued in nxt slide

architecture HA_struct of halfadder is
component XOR2 --defining the ports of 2input XOR gates
port(I1,I2:in std_logic;
O1:out std_logic);
end component;

Component AND2 --defining the ports of 2input AND gates

port(I1,I2:in std_logic;
O2:out std_logic);
end component;

begin
X1: XOR2 port map(a,b,s);
A1: AND2 port map(a,b,c);
end HA_struct;
Full adder
 Full adder- data flow model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
port( x,y,cin: in std_logic;
sum,carry: out std_logic);
end fulladder;
 Full adder- data flow model cont…
architecture FA_dtflo of fulladder is
signal s0,c0,c1: std_logic;
begin
s0<= x XOR y;
c0<= x AND y;
sum<= s0 XOR cin;
c1<= s0 AND cin;
carry<= c0 OR c1;
end FA_dtflo;
 Coding for full adder- structural
• Component half adder is used here

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
port( x,y,cin: in std_logic;
sum,carry: out std_logic);
end fulladder;
 Full adder-struct cont…
architecture FA_struct of fulladder is
Component HA --defining halfadder
port(I1,I2:in std_logic;
O1,O2:out std_logic);
end component;

Component OR2 --defining the ports of 2input AND gates

port(I1,I2:in std_logic;
O1:out std_logic);
end component;
 Full adder-struct cont…
for all:HA use entity work.bind22(HA);
for all:OR2 use entity work.bind2(OR2);
signal s0,c0,c1: std_logic;
Begin
HA1: HA port map(x,y,s0,c0);
HA2: HA port map(s0,cin,sum,c1);
R1:OR2 port map(c0,c1,carry);
end FA_struct;
4:1 MUX – data flow model
4:1 MUX – data flow model contn…
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
port( e,s1,s0,i0,i1,i2,i3: in std_logic;
z: out std_logic);
end mux;
4:1 MUX – data flow model contn…
architecture mux_dtflo of mux is
Signal a,b,c,d: std_logic;
Begin
a<= e AND NOT(s1) AND NOT(s2) AND i0;
b<= e AND NOT(s1) AND s2 AND i1;
c<= e AND (s1) AND NOT(s2) AND i2;
d<= e AND (s1) AND s2 AND i3;
Z<= a OR b OR c OR d;
End mux_dtflo;
Ripple carry adder
 Ripple carry adder cont…
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ripple_carry is
port( x,y: in std_logic_vector(2 down to 0);
cin: in std_logic;
sum: out std_logic_vector(2 down to 0);
cout: out std_logic);
end ripple_carry;
Architecture ripple_carry_adder of ripple_carry is
signal c0,c1: std_logic;
constant delay_gt:time:= 4ns;
begin
sum(0)<=(x(0) XOR y(0)) XOR cin after 2*delay_gt;
sum(1)<=(x(1) XOR y(1) )XOR c0 after 2*delay_gt;
sum(2)<=(x(2) XOR y(2) )XOR c1 after 2*delay_gt;
c0<= (x(0) AND y(0)) OR
(x(0) AND cin) OR
(y(0) AND cin) after 2*delay_gt;
c1<= (x(1) AND y(1)) OR
(x(1) AND c0) OR
(y(0) AND cin) after 2*delay_gt;
End mux_dtflo;
Coding for AND gate
Coding for buffer
Coding for Multiplexer-
data flow model
Coding for Multiplexer-
Behavioural model
Coding for Multiplexer-
structural model
Coding for Multiplexer-
sequential model
Coding for Full adder
Structural coding: example
4-bit binary adder
 Packages and libraries
• Convenient way of referring frequently used
functions.
• Package consists
Use of library functions in packages
2 input NOR gate function is available in the
library as NOR2;
To access component in the library, we ve to
use ‘ library’ st and ‘use’ st.
Use of library functions in packages
D flipflop without Asynchronous input and with
asynchronous input (clear)
Code for JK flipflop