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HDL LAB MANUAL

As Per VTU CBCS Syllabus
5TH SEM ELECTONICS AND COMMUNICATION

VISHVAKIRAN R C

2 0 1 9

ELECTRONICS AND COMMUNICATION ENGG DEPT.

 HDL LAB
B.E., V Semester, ELECTRONICS & COMMUNICATION ENGINEERING /
[As per Choice Based Credit System (CBCS) Scheme]
Course Code 17ECL58 CIE Marks 40
Number of 01 Hr Tutorial (Instructions) SEE Marks 60
Lecture + 02 Hours Laboratory = 03
Hours/Week
RBT Levels L1, L2, L3 Exam Hours 03
CREDITS – 02
Course Objectives: This course will enable students to: Familiarize
with the CAD tool to write HDL programs. Understand simulation
and synthesis of digital design. Program FPGAs/CPLDs to
synthesize the digital designs. Interface hardware to programmable
ICs through I/O ports. Choose either Verilog or VHDL for a given
Note:Abstraction
Programminglevel.
can be done using any compiler. Download the programs on a
FPGA/CPLD boards such as Apex/Acex/Max/Spartan/Sinfi or equivalent and performance
testing may be done using 32 channel pattern generator and logic analyzer apart from
verification by simulation with tools such as Altera/Modelsim or equivalent.
Laboratory Experiments
Part–A: PROGRAMMING
1. Write Verilog code to realize all the logic gates
2. Write a Verilog program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer.
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a VHDL and Verilog code to describe the functions of a Full Adder using three
modeling styles.
4. Write a Verilog code to model 32 bit ALU using the schematic diagram shown
below

ALU should use combinational logic to calculate an output based on the four bit op-
code input.
ALU should pass the result to the out bus when enable line in high, and tri-state the out
bus when the enable line is low.
ALU should decode the 4 bit op-code according to the example given below.
 OPCODE ALU Operation
1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B

5. Develop the Verilog code for the following flip-flops, SR, D, JK and T.
6. Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous
reset) and ―any sequence‖ counters, using Verilog code.

Part–B: INTERFACING (at least four of the following must be covered using
VHDL/Verilog)

1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven
segment display.
3. Write HDL code to control speed, direction of DC and Stepper motor.
4. Write HDL code to accept Analog signal, Temperature sensor and display the
data on LCD or Seven segment display.
5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp
etc.,) using DAC - change the frequency.
6. Write HDL code to simulate Elevator operation.
Course Outcomes: At the end of this course, students should be able to:
Write the Verilog/VHDL programs to simulate Combinational circuits in
Dataflow, Behavioral and Gate level Abstractions.
Describe sequential circuits like flip flops and counters in Behavioral description
and obtain simulation waveforms.
Synthesize Combinational and Sequential circuits on programmable ICs and test the
hardware.
Interface the hardware to the programmable chips and obtain the required
output.

Conduct of Practical Examination:

1. All laboratory experiments are to be included for practical examination.
2. Strictly follow the instructions as printed on the cover page of answer script for
breakup of marks.
3. Change of experiment is allowed only once and Marks allotted to the procedure
part to be made zero.
 CONTENTS

PART A:
PROGRAMMING (Verilog Using Xilinx Tool)
1. Write Verilog code to realize all the logic gates ............................................................................ 1
Write a Verilog program for the following combinational designs............................................ 3-16
2. 2 to 4 decoder .................................................................................................................................. 3
3. 8 to 3 encoder without priority ........................................................................................................ 5
4. 8 to 3 encoder with priority ............................................................................................................. 7
5. 8 to 1 multiplexer ............................................................................................................................ 9
6. 4 bit binary to gray converter ....................................................................................................... 11
7. De-multiplexer............................................................................................................................... 14
8. Comparator ................................................................................................................................... 16
9. a. Write a Verilog code to describe the functions of a Full Adder Using 3 modeling styles . 18-20
i. Full Adder Data Flow Description ......................................................................................... 18
ii. Full Adder Behavioral Description ........................................................................................ 19
iii. Full Adder Structural Description .......................................................................................... 20
b. Write a VHDL code to describe the functions of a Full Adder Using 3 modeling styles .. 22-27
i. Full Adder Data Flow Description ......................................................................................... 22
ii. Full Adder Behavioral Description ........................................................................................ 23
iii. Full Adder Structural Description .......................................................................................... 24
10. Write a model for 32 bit ALU using the schematic diagram
shown below A (31:0) B (31:0) ................................................................................................... 28
 ALU should use combinational logic to calculate an output based on the four-bit
op-code input.
 ALU should pass the result to the out bus when enable line in high, and tri-state the out bus
when the enable line is low.
 ALU should decode the 4 bit op-code according to the given in example below.
OPCODE ALU OPERATION
0. A+B
1. A–B OPCODE
ALU
2. A OR B
OPERATION
3. A AND B ENABLE
4. A Complement
5. A×B
6. A XOR B
7. A NAND B
Develop the Verilog code for the following flip-flops, SR, D, JK and T......................................... 31-38
11. SR Flip Flop ................................................................................................................................. 31
12. JK Flip Flop .................................................................................................................................. 33
13. D Flip Flop ................................................................................................................................... 35
14. T Flip Flop .................................................................................................................................... 37

i
 Design a 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and
“any sequence” counters, using Verilog code................................................................................ 39-47
15. Binary Synchronous Reset 4bit Counter ...................................................................................... 39
16. Binary Asynchronous Reset 4bit Counter .................................................................................... 41
17. BCD Synchronous Reset 4bit Counter ......................................................................................... 43
18. BCD Asynchronous Reset 4bit Counter ....................................................................................... 45
19. Binary Any Sequence up down 4bit Counter ............................................................................... 47

PART B:
INTERFACING (at least four of the following must be covered using VHDL/Verilog)
Write HDL code to display messages on the given seven segment display and LCD and accepting Hex
keypad input data ............................................................................................................................ 49-56
1. 7 Segment Display ........................................................................................................................ 49
2. LCD Display ................................................................................................................................. 53
Write HDL code to control speed, direction of DC and Stepper motor ........................................ 57-62
3. Stepper Motor ............................................................................................................................... 57
4. DC Motor ..................................................................................................................................... 60
5. Write HDL code to generate different waveforms (Sine, Square, Triangle,
Ramp etc.,) using DAC change the frequency and amplitude ............................................... 63-72
i. Sine Wave .............................................................................................................................. 63
ii. Square Wave .......................................................................................................................... 67
iii. Triangle Wave ........................................................................................................................ 69
iv. Positive Ramp ........................................................................................................................ 71
v. Negative Ramp ....................................................................................................................... 72

Weblink:
https://drive.google.com/file/d/0B1DE8wa5nPe0Um4zZlhwbnVqNjg/view?usp=sharing
https://www.scribd.com/document/393126020/HDL-Manual-2019-5th-Sem-E-CE-17ECL58

ii
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
1. ALL LOGIC GATES
not_op
a_in and_op
ALL nand_op
inputs LOGIC outputs
or_op
GATES nor_op
b_in xor_op
xnor_op
Figure 1: Block Diagram of All Logic Gates
not_op

a_in
and_op
b_in

nand_op

or_op

nor_op

xor_op

xnor_op

Logic Diagram of All Gates

Inputs Outputs
not_op
a_in b_in and_op nand_op or_op nor_op xor_op xnor_op
(a_in)
0 0 1 0 1 0 1 0 1
0 1 1 0 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 0 1 0 1 0 0 1
Truth Table 1: All Logic Gates
Verilog File Name: alg.v
// All Logic Gates
module allgates( a_in, b_in, not_op, and_op, nand_op, or_op,
nor_op, xor_op, xnor_op );
input a_in, b_in;
output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;

assign not_op = ~(a_in);

assign and_op = a_in & b_in;
assign nand_op = ~(a_in & b_in);
assign or_op = a_in | b_in;
assign nor_op = ~(a_in | b_in);
assign xor_op = a_in ^ b_in;
assign xnor_op = ~(a_in ^ b_in);

endmodule

Verilog Testbench File Name: alg_test.v

module alg_tb;
reg ain, bin;
wire ynot, yand, ynand, yor, ynor, yxor, yxnor;
PART-A: NON-INTERFACING 1 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

// Instantiate the Unit Under Test (UUT)

allgates uut ( .a_in(ain), .b_in(bin), .not_op(ynot),

.and_op(yand), .nand_op(ynand), .or_op(yor), .nor_op(ynor),
.xor_op(yxor), .xnor_op(yxnor) );

initial
begin
ain = 0; bin = 0;
#10 bin = 1;
#10 ain = 1; bin = 0;
#10 bin = 1;
end

initial #40 $finish;

initial $monitor ($time,” %b %b %b %b %b %b %b %b %b “,ain,bin,

ynot, yand, ynand, yor, ynor, yxor, yxnor);

endmodule

Waveform 1: All Gates

0 0 0 1 0 1 0 1 0 1
10 0 1 1 0 1 1 0 1 0
20 1 0 0 0 1 1 0 1 0
30 1 1 0 1 0 1 0 0 1
Stopped at time : 40 ns

Transcript 1: All Gates

PART-A: NON-INTERFACING 2 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
2. Decoder 2 to 4
2
d_in

inputs 4
Decoder 2 to 4 d_op
outputs
en

Figure 2: Block Diagram of Decoder 2 to 4

Inputs Outputs
en d_in(1) d_in(0) d_op(3) d_op(2) d_op(1) d_op(0)
1 X X Z Z Z Z
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
Truth Table 2: Decoder 2 to 4

Verilog File Name: decoder2to4.v

// decoder2to4
module decoder2to4( en, d_in, d_op );
input [1:0] d_in;
input en;
output [3:0] d_op;
wire en;
wire [1:0] d_in;
reg [3:0] d_op;

always @ (en, d_in)

begin
if(en) // Active Low Enabled
d_op = 4'bZZZZ;
else
begin
case (d_in)
2'b00 : d_op = 4'b0001;
2'b01 : d_op = 4'b0010;
2'b10 : d_op = 4'b0100;
2'b11 : d_op = 4'b1000;
default : d_op = 4'bZZZZ;
endcase
end
end
endmodule

Verilog Testbench File Name: decoder_test.v

module dec_tb;
reg [1:0] din;
reg en;

PART-A: NON-INTERFACING 3 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
wire [3:0] dout;

decoder2to4 uut ( .d_in(din), .en(en), .d_op(dout) );

initial
begin // Initialize Inputs
en = 1;
#10 en = 0; din = 2’b00;
#10 din = 2’b01;
#10 din = 2’b10;
#10 din = 2’b11;
#10 en = 1; din = 2’b10;
end

initial #60 $finish;

initial $monitor ($time,” %b %b %b “,en, din, dout);

endmodule

Waveform 2: Decoder 2 to 4

0 1 xx zzzz
10 0 00 0001
20 0 01 0010
30 0 10 0100
40 0 11 1000
50 1 10 zzzz
Stopped at time : 60 ns
Transcript 2: Decoder 2 to 4

PART-A: NON-INTERFACING 4 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
3. Encoder Without Priority
8
a_in

inputs Encoder 3
y_op
Without Priority
outputs
en

Figure 3: Block Diagram of Encoder Without Priority

Inputs Outputs
y_op y_op y_op
en a_in(7) a_in(6) a_in(5) a_in(4) a_in(3) a_in(2) a_in(1) a_in(0)
(2) (1) (0)

1 X X X X X X X X Z Z Z

0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 1 0 0 0 0 1 1

0 0 0 0 1 0 0 0 0 1 0 0

0 0 0 1 0 0 0 0 0 1 0 1

0 0 1 0 0 0 0 0 0 1 1 0

0 1 0 0 0 0 0 0 0 1 1 1
Truth Table 3: Encoder Without Priority
Verilog File Name: encd_wo_prior.v
// encoder without priority
module encd_wo_prior( en, a_in, y_op );
input en;
input [7:0] a_in;
output [2:0] y_op;
wire en;
wire [7:0] a_in;
reg [2:0] y_op;

always @ (a_in, en)

begin
if(en) //Active Low Enabled
y_op = 3'bZZZ;
else
begin
case (a_in)
8'b00000001 : y_op = 3'b000;

PART-A: NON-INTERFACING 5 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
8'b00000010 : y_op = 3'b001;
8'b00000100 : y_op = 3'b010;
8'b00001000 : y_op = 3'b011;
8'b00010000 : y_op = 3'b100;
8'b00100000 : y_op = 3'b101;
8'b01000000 : y_op = 3'b110;
8'b10000000 : y_op = 3'b111;
default : y_op = 3'bZZZ;
endcase
end
end
endmodule

Verilog Testbench File Name: encd_wo_ptest.v

module encd_wop_tb;
reg [7:0] ain;
reg en;
wire [2:0] yout;
encd_wo_prior uut (.a_in(ain),.en(en),.y_op(yout));
initial
begin
en = 1;
#10 en = 0;
#10 ain =8'b10000000 ;
#10 ain =8'b01000000 ;
#10 ain =8'b00100000 ;
#10 ain =8'b00010000 ;
#10 ain =8'b00001000 ;
#10 ain =8'b00000100 ;
#10 ain =8'b00000010 ;
#10 ain =8'b00000001 ;
#10 ain =8'b10000001 ;
#10 ain =8'b00011101 ;
end
initial #120 $finish;
initial $monitor ($time," %b %b %b ",en, ain, yout);
endmodule

Waveform 3: Encoder Without Priority

0 1 xxxxxxxx zzz
10 0 xxxxxxxx zzz
20 0 10000000 111
30 0 01000000 110
40 0 00100000 101
50 0 00010000 100
60 0 00001000 011
70 0 00000100 010
80 0 00000010 001
90 0 00000001 000
100 0 10000001 zzz
110 0 00011101 zzz
Stopped at time : 120 ns
Transcript 3: Encoder Without Priority

PART-A: NON-INTERFACING 6 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
4. Encoder With Priority
8
a_in

inputs Encoder 3
y_op
With Priority
outputs
en

Figure 4: Block Diagram of Encoder With Priority

Inputs Outputs
y_op y_op y_op
en a_in(7) a_in(6) a_in(5) a_in(4) a_in(3) a_in(2) a_in(1) a_in(0)
(2) (1) (0)
1 X X X X X X X X Z Z Z
0 1 X X X X X X X 1 1 1
0 0 1 X X X X X X 1 1 0
0 0 0 1 X X X X X 1 0 1
0 0 0 0 1 X X X X 1 0 0
0 0 0 0 0 1 X X X 0 1 1
0 0 0 0 0 0 1 X X 0 1 0
0 0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 0 0 0 1 0 0 0
Truth Table 4: Encoder With Priority
Verilog File Name: encd_w_prior.v
// encoder with priority
module encd_w_prior( en, a_in, y_op );
input en;
input [7:0] a_in;
output [2:0] y_op;
wire en;
wire [7:0] a_in;
reg [2:0] y_op;

always @ (a_in, en)

begin
if (en == 1'b1) // Active Low Enabled
y_op = 3'bZZZ;
else
begin
if(a_in[7] == 1'b1) y_op = 3'b111;
else if(a_in[6] == 1'b1) y_op = 3'b110;
else if(a_in[5] == 1'b1) y_op = 3'b101;
else if(a_in[4] == 1'b1) y_op = 3'b100;
else if(a_in[3] == 1'b1) y_op = 3'b011;
else if(a_in[2] == 1'b1) y_op = 3'b010;
else if(a_in[1] == 1'b1) y_op = 3'b001;

PART-A: NON-INTERFACING 7 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
else if(a_in[0] == 1'b1) y_op = 3'b000;
else y_op = 3'bZZZ;
end
end
endmodule

Verilog Testbench File Name: encd_w_ptest.v

module encd_wp_tb;
reg [7:0] ain;
reg en;
wire [2:0] yout;
encd_w_prior uut (.a_in(ain),.en(en),.y_op(yout));
initial
begin
en = 1;
#10 en = 0;
#10 ain =8'b10000000 ;
#10 ain =8'b01000000 ;
#10 ain =8'b00100000 ;
#10 ain =8'b00010000 ;
#10 ain =8'b00001000 ;
#10 ain =8'b00000100 ;
#10 ain =8'b00000010 ;
#10 ain =8'b00000001 ;
#10 ain =8'b10000001 ;
#10 ain =8'b00011101 ;
end
initial #120 $finish;
initial $monitor ($time," %b %b %b ",en, ain, yout);
endmodule

Waveform 4: Encoder With Priority

0 1 xxxxxxxx zzz
10 0 xxxxxxxx zzz
20 0 10000000 111
30 0 01000000 110
40 0 00100000 101
50 0 00010000 100
60 0 00001000 011
70 0 00000100 010
80 0 00000010 001
90 0 00000001 000
100 0 10000001 111
110 0 00011101 100
Stopped at time : 120 ns
Transcript 4: Encoder With Priority

PART-A: NON-INTERFACING 8 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
5. Multiplexer 8 to 1
8
i_in

inputs y_out
Multiplexer 8 to 1
output
en

3
sel
Figure 5: Block Diagram of Multiplexer 8 to 1

Inputs Output
sel sel sel i_in i_in i_in i_in i_in i_in i_in i_in
en y_out
(2) (1) (0) (7) (6) (5) (4) (3) (2) (1) (0)
1 X X X X X X X X X X X Z
0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 0 0 1
0 0 1 1 0 0 0 0 1 0 0 0 1
0 1 0 0 0 0 0 1 0 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 1 0 0 1 0 0 0 0 0 0 1
0 1 1 1 1 0 0 0 0 0 0 0 1
Truth Table 5: Mux 8 to 1
Verilog File Name: mux8to1.v
// Multiplexer 8 to 1
module mux8to1(en,i_in,sel,y_out);
input en;
input [2:0] sel;
input [7:0] i_in;
output y_out;
wire en;
wire [7:0] i_in;
wire [2:0] sel;
reg y_out;

always@(en,sel,i_in)
begin
if(en != 0) // Active Low Enabled
y_out = 1'bZ;
else
begin
case(sel)
3'b000: y_out = i_in[0];
3'b001: y_out = i_in[1];
3'b010: y_out = i_in[2];
3'b011: y_out = i_in[3];
3'b100: y_out = i_in[4];
PART-A: NON-INTERFACING 9 RCVK
 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
3'b101: y_out = i_in[5];
3'b110: y_out = i_in[6];
3'b111: y_out = i_in[7];
default: y_out = 1'bZ;
endcase
end
end
endmodule

Verilog Testbench File Name: mux81_test.v

module mux81_tb;
reg en;
reg [7:0] i_in;
reg [2:0] sel;
wire yout;
mux8to1 uut (.en(en),.i_in(i_in),.sel(sel),.y_out(yout));
initial
begin
en = 1;
#10 en = 0;
#10 i_in = 8'b01000010; sel = 3'b001;
#10 i_in = 8'b00000100; sel = 3'b010;
#10 i_in = 8'b00001000; sel = 3'b011;
#10 i_in = 8'b00010000; sel = 3'b100;
#10 i_in = 8'b00100000; sel = 3'b101;
#10 i_in = 8'b01000000; sel = 3'b001;

end
initial #80 $finish;
initial $monitor ($time," %b %b %b %b ",en, i_in, sel, yout);
endmodule

Waveform 5: Mux 8 to 1

0 1 xxxxxxxx xxx z
10 0 xxxxxxxx xxx z
20 0 01000010 001 1
30 0 00000100 010 1
40 0 00001000 011 1
50 0 00010000 100 1
60 0 00100000 101 1
70 0 01000000 001 0
Stopped at time : 80 ns
Transcript 5: Multiplexer 8 to 1

PART-A: NON-INTERFACING 10 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
6. 4Bit Binary to Gray Converter

Binary
inputs 4
to g_op
4
b_in Gray
outputs
Converter

Figure 6: Block Diagram of Binary to Gray Converter

b_in(0)
b_in(1)
g_op(0) Boolean Expressions
𝑔_𝑜𝑝(3) = 𝑏_𝑖𝑛(3)
b_in(2)
g_op(1) 𝑔_𝑜𝑝(2) = 𝑏_𝑖𝑛(3)⨁ 𝑏_𝑖𝑛(2)
𝑔_𝑜𝑝(1) = 𝑏_𝑖𝑛(2)⨁ 𝑏_𝑖𝑛(1)
b_in(3)
g_op(2) 𝑔_𝑜𝑝(0) = 𝑏_𝑖𝑛(1)⨁ 𝑏_𝑖𝑛(0)
g_op(3)

Logic Diagram of 4bits Binary to Gray

Converter

Inputs Outputs
Binary Gray
Decimal
b_in(3) b_in(2) b_in(1) b_in(0) g_op(3) g_op(2) g_op(1) g_op(0)
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Truth Table 6: Binary to Gray
Verilog File Name: bin_to_gray_4bit.v
// Binary to Gray 4bit Converter
module bin_to_gray_4bit( b_in, g_op );
input [3:0] b_in;
output [3:0] g_op;
wire [3:0] b_in;
reg [3:0] g_op;

always @ (b_in)
begin

PART-A: NON-INTERFACING 11 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
g_op[3] = b_in[3];
g_op[2] = b_in[3] ^ b_in[2];
g_op[1] = b_in[2] ^ b_in[1];
g_op[0] = b_in[1] ^ b_in[0];
end
endmodule

Verilog Testbench File Name: b2g_4bit_test.v

module bitogr_tb;
reg [3:0] bin;
wire [3:0] gout;
bin_to_gray_4bit uut (.b_in(bin), .g_op(gout) );
initial
begin
bin=0;
#10 bin=1;
#10 bin=2;
#10 bin=3;
#10 bin=4;
#10 bin=5;
#10 bin=6;
#10 bin=7;
#10 bin=8;
#10 bin=9;
#10 bin=10;
#10 bin=11;
#10 bin=12;
#10 bin=13;
#10 bin=14;
#10 bin=15;
end
initial #160 $finish;
initial $monitor ($time," %b %b ",bin, gout);
endmodule

Waveform 6: 4Bit Binary to Gray Converter

PART-A: NON-INTERFACING 12 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

0 0000 0000
10 0001 0001
20 0010 0011
30 0011 0010
40 0100 0110
50 0101 0111
60 0110 0101
70 0111 0100
80 1000 1100
90 1001 1101
100 1010 1111
110 1011 1110
120 1100 1010
130 1101 1011
140 1110 1001
150 1111 1000
Stopped at time : 160 ns
Transcript 6: 4Bit Binary to Gray Converter

PART-A: NON-INTERFACING 13 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
7. Demultiplexer 1 to 4

en

inputs
4 y_out
2 Demultiplexer 1 to 4
sel outputs
a_in

Figure 7: Block Diagram of Demultiplexer 1 to 4

Inputs Outputs
sel sel y_out y_out y_out y_out
en a_in
(1) (0) (3) (2) (1) (0)
1 X X X Z Z Z Z
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 1 0 1 0 1 0 0
0 1 1 1 1 0 0 0
Truth Table 7: Demux 1 to 4
Verilog File Name: demux1to4.v
// Demultiplexer 1 to 4
module demux1to4(en,sel,a_in,y_out);
input en;
input [1:0] sel;
input a_in;
output [3:0] y_out;
wire en;
wire [1:0] sel;
wire a_in;
reg [3:0] y_out;

always@(en,sel,a_in)
begin
if(en != 0) // Active Low Enabled
y_out = 4'bZZZZ;
else
begin
y_out = 4'b0000;
case(sel)
2'b00 : y_out[0] = a_in;
2'b01 : y_out[1] = a_in;
2'b10 : y_out[2] = a_in;
2'b11 : y_out[3] = a_in;
default : y_out = 4'bZZZZ;
endcase
end
end
endmodule

PART-A: NON-INTERFACING 14 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog Testbench File Name: demux1to4_test.v
module demux_tb;
reg en, ain;
reg [1:0] sel;
wire [3:0] yout;
demux1to4 uut ( .sel(sel),.en(en),.a_in(ain), .y_out(yout));
initial
begin
en = 1;
#10 en = 0;
sel = 2'b00; ain = 1;
#10 sel = 2'b10; ain = 1;
#10 sel = 2'b01; ain = 1;
#10 sel = 2'b01; ain = 1'bX;
#10 sel = 2'b11; ain = 1;
end
initial #60 $finish;
initial $monitor ($time," %b %b %b %b ",en, ain, sel, yout);
endmodule

Waveform 7: Demultiplexer 1 to 4

0 1 x xx zzzz
10 0 1 00 0001
20 0 1 10 0100
30 0 1 01 0010
40 0 x 01 00x0
50 0 1 11 1000
Stopped at time : 60 ns
Transcript 7: Demultiplexer 1 to 4

PART-A: NON-INTERFACING 15 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
8. 4Bit Comparator

4 g_op
a_in
outputs
Comparator 4bit L_op
inputs
4 e_op
b_in

Figure 8: Block Diagram of Comparator 4bit

Outputs
Inputs
a_in > b_in a_in = b_in a_in < b_in
a_in b_in g_op e_op L_op
---- ---- Z Z Z
1100 0011 1 0 0
0110 0110 0 1 0
1000 1110 0 0 1
Truth Table 8: Comparator 4Bits
Verilog File Name: comparator4bit.v
// Comparator 4bit
module comparator4bit( a_in,b_in,g_op,L_op,e_op);
input [3:0] a_in,b_in;
output g_op,L_op,e_op;
wire [3:0] a_in,b_in;
reg g_op,L_op,e_op;

always@(a_in,b_in)
if( a_in > b_in)
begin
g_op = 1; L_op = 0; e_op = 0;
end
else if( a_in < b_in)
begin
g_op = 0; L_op = 1; e_op = 0;
end
else if( a_in == b_in)
begin
g_op = 0; L_op = 0; e_op = 1;
end
else
begin
g_op = 1'bZ; L_op = 1'bZ; e_op = 1'bZ;
end
endmodule

Verilog Testbench File Name: compar_4bit_test.v

module comp4bit_tb;
reg [3:0] ain,bin;
wire grt,Less,equ;

PART-A: NON-INTERFACING 16 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
comparator4bit uut(.a_in(ain), .b_in(bin), .g_op(grt), .L_op(Less),
.e_op(equ) );

initial
begin
ain = 4'b1100; bin = 4'b0011;
#10 ain = 4'b0110; bin = 4'b0110;
#10 ain = 4'b1000; bin = 4'b1110;
#10 ain = 4'b0000; bin = 4'b0001;
end
initial #40 $finish;
initial $monitor ($time," %b %b %b %b %b",ain,
bin,grt,Less,equ);

endmodule

Waveform 8: 4Bit Comparator

0 1100 0011 1 0 0
10 0110 0110 0 0 1
20 1000 1110 0 1 0
30 0000 0001 0 1 0
Stopped at time : 40 ns
Transcript 8: 4Bit Comparator

PART-A: NON-INTERFACING 17 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
9. Full Adder – a. Verilog Module

a_in sum
b_in Full Adder outputs
inputs
c_in carry

Figure 9a: Block Diagram of Full Adder

a_in S1
b_in x1 sum
x2

a2
S3
carry
o1
a1
S2
c_in

Logic Diagram of Full Adder

Inputs Outputs
a_in b_in c_in sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Truth Table 9a: Full Adder
Full Adder Data Flow Description

Verilog File Name: FullAdder_DF.v

// FullAdder - Data Flow Model
module fulladder_df( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;

assign sum = a_in ^ b_in ^ c_in;

assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in);
endmodule

Verilog Testbench File Name: full_adder_test.v

`timescale 1ns/1ps
module fulladd_tb;
PART-A: NON-INTERFACING 18 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
reg ain, bin, cin;
wire sum, carry;

fulladder_df uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0;

#1 ain = 0; bin = 0; cin = 1;
#1 ain = 0; bin = 1; cin = 0;
#1 ain = 0; bin = 1; cin = 1;
#1 ain = 1; bin = 0; cin = 0;
#1 ain = 1; bin = 0; cin = 1;
#1 ain = 1; bin = 1; cin = 0;
#1 ain = 1; bin = 1; cin = 1;
#1 ain = 0; bin = 0; cin = 0;

end
initial #9 $finish;
initial $monitor ($time," %b%b%b --> %b,%b", ain, bin, cin, sum,
carry);
endmodule

Full Adder Behavioral Description

Verilog File Name: FullAdder_Behav.v

//FullAdder - Behavioral Model
module fulladder_behav( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
wire a_in, b_in, c_in;
reg sum, carry;

always @ ( a_in, b_in, c_in)

begin
if(a_in==0 & b_in==0 & c_in==0)
begin
sum = 0;
carry = 0;
end
else if (( a_in==0 & b_in==0 & c_in == 1)
| (a_in==0 & b_in==1 & c_in == 0)
| (a_in==1 & b_in==0 & c_in == 0))
begin
sum = 1;
carry = 0;
end

else if (( a_in==0 & b_in==1 & c_in == 1)

| (a_in==1 & b_in==0 & c_in == 1)
| (a_in==1 & b_in==1 & c_in == 0))
begin
sum = 0;
carry = 1;

PART-A: NON-INTERFACING 19 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
end
else if(a_in==1 & b_in==1 & c_in == 1)
begin
sum = 1;
carry = 1;
end
end
endmodule

Verilog Testbench File Name: full_adder_test.v

`timescale 1ns/1ps
module fulladd_tb;
reg ain, bin, cin;
wire sum, carry;

fulladder_behav uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0;

#1 ain = 0; bin = 0; cin = 1;
#1 ain = 0; bin = 1; cin = 0;
#1 ain = 0; bin = 1; cin = 1;
#1 ain = 1; bin = 0; cin = 0;
#1 ain = 1; bin = 0; cin = 1;
#1 ain = 1; bin = 1; cin = 0;
#1 ain = 1; bin = 1; cin = 1;
#1 ain = 0; bin = 0; cin = 0;

end
initial #9 $finish;
initial $monitor ($time," %b%b%b --> %b,%b", ain, bin, cin, sum,
carry);
endmodule

Full Adder Structural Description

Verilog File Name: full_adder_struct.v

//Full Adder - Structural
module full_adder( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
wire s1,s2,s3;

//syntax: gate_operator lable (ouput, input, input, , , );

half_adder HA1 (s1, s2, a_in, b_in);
half_adder HA2 (sum, s3, s1, c_in);
or O1 (carry, s2, s3);
endmodule
Verilog File Name: half_adder_dataflow.v
//Half Adder - Dataflow
module half_adder( sum, carry, a_in, b_in );
input a_in, b_in;

PART-A: NON-INTERFACING 20 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
output sum, carry;

assign sum = a_in ^ b_in;

assign carry = a_in & b_in;

endmodule

Verilog Testbench File Name: full_adder_test.v

`timescale 1ns/1ps
module fulladd_tb;
reg ain, bin, cin;
wire sum, carry;

full_adder uut (.a_in(ain), .b_in(bin), .c_in(cin),

.sum(sum),.carry(carry));
initial
begin

ain = 0; bin = 0; cin = 0;

#1 ain = 0; bin = 0; cin = 1;
#1 ain = 0; bin = 1; cin = 0;
#1 ain = 0; bin = 1; cin = 1;
#1 ain = 1; bin = 0; cin = 0;
#1 ain = 1; bin = 0; cin = 1;
#1 ain = 1; bin = 1; cin = 0;
#1 ain = 1; bin = 1; cin = 1;
#1 ain = 0; bin = 0; cin = 0;

end
initial #9 $finish;
initial $monitor ($time," %b%b%b --> %b,%b", ain, bin, cin, sum,
carry);
endmodule

Waveform 9a: Full Adder

0 000 --> 0,0

1 001 --> 1,0
2 010 --> 1,0
3 011 --> 0,1
4 100 --> 1,0
5 101 --> 0,1
6 110 --> 0,1
7 111 --> 1,1
8 000 --> 0,0
Stopped at time : 9 ns
Transcript 9a: Full Adder

PART-A: NON-INTERFACING 21 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
9. Full Adder – b. VHDL Module

ain sum
bin Full Adder outputs
inputs
cin carry

Figure 9b: Block Diagram of Full Adder

ain S1
bin x1 sum
x2

a2
S3
carry
o1
a1
S2
cin

Logic Diagram of Full Adder

Inputs Outputs
ain bin cin sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Truth Table 9b: Full Adder
Full Adder Data Flow Description

VHDL File Name: FullAdder_DF.vhd

// FullAdder - Data Flow Model
-- Module Name: full_adder - dataflow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
Port ( ain, bin, cin : in STD_LOGIC;
sum, carry : out STD_LOGIC);
end full_adder;
architecture dataflow of full_adder is
begin
sum <= ain xor bin xor cin;
PART-A: NON-INTERFACING 22 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
carry <= ((ain and bin) or (cin and (ain xor bin)));
end dataflow;

VHDL Testbench File Name: full_adder_test.vhd

-- module name: full_adder - testbench

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_test is
end full_adder_test;

architecture behavior of full_adder_test is

-- component declaration for the unit under test (uut)

component full_adder
port(
ain, bin, cin : in std_logic;
sum, carry : out std_logic);
end component;

--inputs
signal ain, bin, cin : std_logic := '0';

--outputs
signal sum : std_logic;
signal carry : std_logic;

begin

-- instantiate the unit under test (uut)

uut: full_adder port map (
ain => ain, bin => bin, cin => cin, sum => sum, carry => carry
);

-- stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;

ain <= '0'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '1'; wait for 10ns;

end process;

end;

PART-A: NON-INTERFACING 23 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Full Adder Behavioral Description

VHDL File Name: FullAdder_Behav.vhd

-- module name: full_adder - behavioral
library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port ( ain, bin, cin : in std_logic;
sum, carry : out std_logic);
end full_adder;

architecture behavioral of full_adder is

begin
process( ain, bin, cin)
begin
if (ain = '0' and bin = '0' and cin = '0') then sum<='0'; carry <='0';
elsif (ain = '0' and bin = '0' and cin = '1') then sum<='1'; carry <='0';
elsif (ain = '0' and bin = '1' and cin = '0') then sum<='1'; carry <='0';
elsif (ain = '0' and bin = '1' and cin = '1') then sum<='0'; carry <='1';
elsif (ain = '1' and bin = '0' and cin = '0') then sum<='1'; carry <='0';
elsif (ain = '1' and bin = '0' and cin = '1') then sum<='0'; carry <='1';
elsif (ain = '1' and bin = '1' and cin = '0') then sum<='0'; carry <='1';
else sum<='1'; carry <='1';
end if;
end process;

end behavioral;

VHDL Testbench File Name: full_adder_test.vhd

-- module name: full_adder - testbench

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_test is
end full_adder_test;

architecture behavior of full_adder_test is

-- component declaration for the unit under test (uut)

component full_adder
port(
ain, bin, cin : in std_logic;
sum, carry : out std_logic);
end component;
--inputs
signal ain, bin, cin : std_logic := '0';
--outputs
signal sum : std_logic;
signal carry : std_logic;

begin -- instantiate the unit under test (uut)

uut: full_adder port map (
ain => ain,
bin => bin,
cin => cin,
sum => sum,
carry => carry
);

PART-A: NON-INTERFACING 24 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
-- stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
ain <= '0'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '1'; wait for 10ns;
end process;
end;

Full Adder Structural Description

VHDL File Name: full_adder_struct.vhd

-- module name: full_adder - structural
library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port ( ain, bin, cin : in std_logic;
sum, carry : out std_logic);
end full_adder;

architecture structural of full_adder is

signal c1,c2,c3:std_logic;
component xor_3
port(x,y,z : in std_logic;
u : out std_logic);
end component;
component and_2
port(l,m : in std_logic;
n : out std_logic);
end component;
component or_3
port(p,q,r : in std_logic;
s : out std_logic);
end component;
begin
x1: xor_3 port map ( ain, bin, cin, sum);
a1: and_2 port map ( ain, bin, c1);
a2: and_2 port map ( bin, cin, c2);
a3: and_2 port map ( ain, cin, c3);
o1: or_3 port map (c1, c2, c3, carry);

end structural;

PART-A: NON-INTERFACING 25 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
VHDL File Name: xor_gate_3_ip.vhd
-- module name: xor_3 - dataflow
library ieee;
use ieee.std_logic_1164.all;

entity xor_3 is
port ( x,y,z : in std_logic;
u : out std_logic);
end xor_3;

architecture dataflow of xor_3 is

begin
u<=(x xor y) xor z;
end dataflow;

VHDL File Name: or_gate_3_ip.vhd

-- module name: or_3 - dataflow
library ieee;
use ieee.std_logic_1164.all;

entity or_3 is
port ( p,q,r : in std_logic;
s : out std_logic);
end or_3;

architecture dataflow of or_3 is

begin
s <= (p or q) or r;
end dataflow;

VHDL File Name: and_gate_2_ip.vhd

-- module name: and_2 - dataflow
library ieee;
use ieee.std_logic_1164.all;

entity and_2 is
port ( l,m : in std_logic;
n : out std_logic);
end and_2;

architecture dataflow of and_2 is

begin
n <= l and m;
end dataflow;
VHDL Testbench File Name: full_adder_test.vhd
-- module name: full_adder - testbench

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_test is
end full_adder_test;

architecture behavior of full_adder_test is

-- component declaration for the unit under test (uut)

PART-A: NON-INTERFACING 26 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
component full_adder
port(
ain, bin, cin : in std_logic;
sum, carry : out std_logic);
end component;
--inputs
signal ain, bin, cin : std_logic := '0';
--outputs
signal sum : std_logic;
signal carry : std_logic;

begin -- instantiate the unit under test (uut)

uut: full_adder port map (
ain => ain,
bin => bin,
cin => cin,
sum => sum,
carry => carry
);
-- stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
ain <= '0'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '0'; bin <= '1'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '0'; cin <= '1'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '0'; wait for 10ns;
ain <= '1'; bin <= '1'; cin <= '1'; wait for 10ns;
end process;
end;

Waveform 10a: Full Adder

PART-A: NON-INTERFACING 27 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
10. ALU 32 Bits

32
a_in
ALU 32bits 32
inputs zout
outputs
32
b_in

3
opc
Figure 10: Block Diagram of ALU 32bits
Inputs Outputs Actio
opc a_in b_in zout ns
No
XX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXX ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
Chan
X XXXXXXXXXXXX XXXXXXXXXXX ZZ
ge
a_in +
000 000000000000000000010111 000000000000000000101101 00000000000000000000000001000100
b_in
a_in -
001 000000000000000000010111 000000000000000000101101 11111111111111111111111111101010
b_in
a_in
010 000000000000000000010111 000000000000000000101101 00000000000000000000000000111111 or
b_in
a_in
011 000000000000000000010111 000000000000000000101101 00000000000000000000000000000101 and
b_in
not
100 000000000000000000010111 000000000000000000101101 11111111111111111111111111101000
a_in
a_in *
101 000000000000000000010111 000000000000000000101101 00000000000000000000010000001011
b_in
a_in
110 000000000000000000010111 000000000000000000101101 00000000000000000000000000111010 xor
b_in
a_in
111 000000000000000000010111 000000000000000000101101 11111111111111111111111111111010 nand
b_in
Truth Table 10: ALU 32bits
Verilog File Name: alu32bit.v
// ALU 32bit
`timescale 1ns / 1ps

module alu32bit(a_in,b_in,opcode,zout);
input [23:0] a_in,b_in;
input [2:0] opcode;
output [31:0] zout;
reg [31:0] zout;
wire [31:0] a, b;

assign a = {8'b0,a_in};
assign b = {8'b0,b_in};

always@ *
begin
case (opcode)
3'b000 : zout = a+b;
3'b001 : zout = a-b;
PART-A: NON-INTERFACING 28 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
3'b010 : zout = a | b;
3'b011 : zout = a & b;
3'b100 : zout = ~ a;
3'b101 : zout = a*b;
3'b110 : zout = a ^ b;
3'b111 : zout = ~( a & b );
default : zout = 32'd0;
endcase
end

endmodule
Verilog Testbench File Name: alu32bit_test.v

`timescale 1ns / 1ps

module alu32bit_test;

// Inputs
reg [23:0] a_in;
reg [23:0] b_in;
reg [2:0] opcode;

// Outputs
wire [31:0] zout;

// Instantiate the Unit Under Test (UUT)

alu32bit uut (
.a_in(a_in),
.b_in(b_in),
.opcode(opcode),
.zout(zout)
);

initial begin
// Initialize Inputs
a_in = 23; b_in = 45;
opcode = 0;
#1 opcode = 1;
#1 opcode = 2;
#1 opcode = 3;
#1 opcode = 4;
#1 opcode = 5;
#1 opcode = 6;
#1 opcode = 7;
#1 a_in = 53; b_in = 56;
#1 opcode = 0;
#1 opcode = 1;
#1 opcode = 2;
#1 opcode = 3;
#1 opcode = 4;
#1 opcode = 5;
#1 opcode = 6;
#1 opcode = 7;
end

PART-A: NON-INTERFACING 29 RCVK

5TH SEM, HDL Lab, 17ECL58
initial #20 $finish;
initial $monitor ($time," %b %b %b ====> %b " , a_in,b_in,opcode,zout);
endmodule
Finished
0 000000000000000000010111
1 000000000000000000010111
2 000000000000000000010111
3 000000000000000000010111
4 000000000000000000010111
5 000000000000000000010111
6 000000000000000000010111
7 000000000000000000010111
8 000000000000000000110101
9 000000000000000000110101
Stopped at time : 20ns
PART-A: NON-INTERFACING
2019-20 DEPT. E&C, CEC, Bengaluru
circuit initialization process.
000000000000000000101101 000 ====> 00000000000000000000000001000100
000000000000000000101101 001 ====> 11111111111111111111111111101010
000000000000000000101101 010 ====> 00000000000000000000000000111111
000000000000000000101101 011 ====> 00000000000000000000000000000101
000000000000000000101101 100 ====> 11111111111111111111111111101000
000000000000000000101101 101 ====> 00000000000000000000010000001011
000000000000000000101101 110 ====> 00000000000000000000000000111010
000000000000000000101101 111 ====> 11111111111111111111111111111010
000000000000000000111000 111 ====> 11111111111111111111111111001111
000000000000000000111000 000 ====> 00000000000000000000000001101101
Transcript 10: ALU 32 Bits
30 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
11. S R Flip Flop
s
q
r
SR Flip Flop outputs
inputs
qb
rst

clk
Figure 11: Block Diagram of SR Flip Flop

Inputs Outputs
rst clk s r q qb Action
1 ↑ X X q qb No Change
0 ↑ 0 0 q qb No Change
0 ↑ 0 1 0 1 Reset
0 ↑ 1 0 1 0 Set
0 ↑ 1 1 - - Illegal
Truth Table 11: S R Flip Flop
Verilog File Name: sr_ff.v
//Async SR Flip Flop
module sr_ff( sr , clk , reset , q ,qb );
input [1:0] sr;
input clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (sr)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = 1'bX;
endcase
qb = ~q;
end
endmodule

PART-A: NON-INTERFACING 31 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog Testbench File Name: sr_ff_test.v
`timescale 1ns/1ps
module srflip_tb;
reg clk, rst;
reg [1:0] sr;
wire q, qb;

sr_ff uut ( .clk(clk), .reset(rst), . sr(sr), .q(q), .qb(qb));

initial
begin
clk = 0; rst=1; sr=2'b00;
end
always
#5 clk=~clk;
initial
begin
#10; rst=0;
#10 sr = 2'b10;
#10 sr = 2'b00;
#10 sr = 2'b01;
#10 sr = 2'b11;
#20 sr = 2'b10;
#10 sr = 2'b00;

end
initial #90 $finish;
initial $monitor ($time,” %b %b %b %b%b ”,clk,rst,sr,q,qb);
endmodule

Waveform 11: S R Flip Flop

0 0 1 00 01
5 1 1 00 01
10 0 0 00 01
15 1 0 00 01
20 0 0 10 01
25 1 0 10 10
30 0 0 00 10
35 1 0 00 10
40 0 0 01 10
45 1 0 01 01
50 0 0 11 01
55 1 0 11 xx
60 0 0 11 xx
65 1 0 11 xx
70 0 0 10 xx
75 1 0 10 10
80 0 0 00 10
85 1 0 00 10
Stopped at time : 90 ns
Transcript 11: S R Flip Flop

PART-A: NON-INTERFACING 32 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

12. J K Flip Flop

j
q
k
JK Flip Flop outputs
inputs
qb
rst

clk
Figure 12: Block Diagram of JK Flip Flop

Inputs Outputs
rst clk j k q qb Action
1 ↑ X X q qb No Change
0 ↑ 0 0 q qb No Change
0 ↑ 0 1 0 1 Reset
0 ↑ 1 0 1 0 Set
0 ↑ 1 1 q' q' Toggle
Truth Table 12: J K Flip Flop
Verilog File Name: jk_ff.v
//Async JK Flip Flop
module jk_ff( jk , clk , reset , q ,qb );
input [1:0] jk;
input clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb = ~q;
end
else
begin
case (jk)
2'd0 : q = q;
2'd1 : q = 1'b0;
2'd2 : q = 1'b1;
2'd3 : q = ~q;
endcase
qb = ~q;
end
endmodule

Verilog Testbench File Name: jk_ff_test.v

`timescale 1ns/1ps
module jkflip_tb;
reg clk, rst;
reg [1:0] jk;
wire q, qb;

PART-A: NON-INTERFACING 33 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

jk_ff uut ( .clk(clk), .reset(rst), . jk(jk), .q(q), .qb(qb));

initial
begin
clk = 0; rst=1; jk=2'b00;
end
always
#5 clk=~clk;
initial
begin
#10; rst=0;
#10 jk = 2'b10;
#10 jk = 2'b00;
#10 jk = 2'b01;
#10 jk = 2'b11;
#40 jk = 2'b10;
#10 jk = 2'b00;

end
initial #110 $finish;
initial $monitor ($time,” %b %b %b %b%b ”,clk,rst,jk,q,qb);
endmodule

Waveform 12: J K Flip Flop

0 0 1 00 01
5 1 1 00 01
10 0 0 00 01
15 1 0 00 01
20 0 0 10 01
25 1 0 10 10
30 0 0 00 10
35 1 0 00 10
40 0 0 01 10
45 1 0 01 01
50 0 0 11 01
55 1 0 11 10
60 0 0 11 10
65 1 0 11 01
70 0 0 11 01
75 1 0 11 10
80 0 0 11 10
85 1 0 11 01
90 0 0 10 01
95 1 0 10 10
100 0 0 00 10
105 1 0 00 10
Stopped at time : 110 ns
Transcript 12: J K Flip Flop

PART-A: NON-INTERFACING 34 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
13. D Flip Flop

d q

D Flip Flop outputs

inputs
qb
rst

clk
Figure 13: Block Diagram of D Flip Flop

Inputs Outputs
rst clk d q qb Action
1 ↑ X q qb No Change
0 ↑ 0 0 1 Reset
0 ↑ 1 1 0 Set
Truth Table 13: D Flip Flop

Verilog File Name: d_ff.v

//Async D Flip Flop
module d_ff( d , clk , reset , q ,qb );
input d, clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb=~q;
end
else
begin
q = d;
qb=~q;
end
endmodule

Verilog Testbench File Name: d_ff_test.v

`timescale 1ns/1ps
module dflip_tb;
reg clk, rst, d;
wire q, qb;
d_ff uut ( .clk(clk), .reset(rst), . d(d), .q(q), .qb(qb));
initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

PART-A: NON-INTERFACING 35 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
initial
begin
#10; rst=0;
#10 d = 0;
#10 d = 1;
#10
#10 d = 0;
#10 d = 1;

end
initial #80 $finish;
initial $monitor ($time,” %b %b %b %b%b ”,clk,rst,d,q,qb);
endmodule

Waveform 13: D Flip Flop

0 0 1 x 01
5 1 1 x 01
10 0 0 x 01
15 1 0 x xx
20 0 0 0 xx
25 1 0 0 01
30 0 0 1 01
35 1 0 1 10
40 0 0 1 10
45 1 0 1 10
50 0 0 0 10
55 1 0 0 01
60 0 0 1 01
65 1 0 1 10
70 0 0 1 10
75 1 0 1 10
Stopped at time : 80 ns
Transcript 13: D Flip Flop

PART-A: NON-INTERFACING 36 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
14. T Flip Flop

t q

T Flip Flop outputs

inputs
qb
rst

clk
Figure 14: Block Diagram of T Flip Flop

Inputs Outputs
rst clk t q qb Action
1 ↑ X q qb No Change
0 ↑ 0 q qb No Change
0 ↑ 1 q' q' Toggle
Truth Table 14: T Flip Flop
Verilog File Name: t_ff.v
//Async T Flip Flop
module t_ff( t, clk, reset, q, qb );
input t, clk, reset ;
output q,qb;
reg q,qb;

always @ ( posedge clk or posedge reset)

if (reset)
begin
q = 1'b0;
qb=~q;
end
else
if (t)
begin
q = ~q;
qb = ~q;
end
endmodule

PART-A: NON-INTERFACING 37 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog Testbench File Name: t_ff_test.v

`timescale 1ns/1ps
module tflip_tb;
reg clk, rst, t;
wire q, qb;
t_ff uut ( .clk(clk), .reset(rst), . t(t), .q(q), .qb(qb));
initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

initial
begin
#10; rst=0;
#10 t = 0;
#10 t = 1;
#20
#10 t = 0;
#10 t = 1;

end
initial #90 $finish;
initial $monitor ($time,” %b %b %b %b%b ”,clk,rst,t,q,qb);
endmodule

Waveform 14: T Flip Flop

0 0 1 x 01
5 1 1 x 01
10 0 0 x 01
15 1 0 x 01
20 0 0 0 01
25 1 0 0 01
30 0 0 1 01
35 1 0 1 10
40 0 0 1 10
45 1 0 1 01
50 0 0 1 01
55 1 0 1 10
60 0 0 0 10
65 1 0 0 10
70 0 0 1 10
75 1 0 1 01
80 0 0 1 01
85 1 0 1 10
Stopped at time : 90 ns
Transcript 14: T Flip Flop

PART-A: NON-INTERFACING 38 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
15. Binary Synchronous Reset 4bit Counter

Binary Synchronous 4
rst bin_out
Reset 4bit Counter outputs
inputs

clk
Figure 15: Block Diagram of Binary Synchronous Reset 4bit
Counter

Verilog File Name: bin_counter_sync_4bit.v

// Binary synchronous reset 4bit counter
module bin_sync_4bit ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end

always @(posedge clk)

if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule

Verilog Testbench File Name: bin_counter_sync_4bit_test.v

`timescale 1ns/1ps
module count4bit_tb;
reg rst, clk;
wire [3:0] count;

bin_sync_4bit uut ( .rst(rst), .clk(clk), .count(count));

initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

PART-A: NON-INTERFACING 39 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

initial
begin
#5; rst=0;
#55;
#10; rst=1;
#5; rst=0;
#30;
#2; rst=1;
#10;
end
initial #120 $finish;
initial $monitor ($time,” %b %b %b ”,clk,rst,count);

endmodule

Waveform 15: Binary Synchronous Reset 4bit Counter

0 0 1 0000
5 1 0 0001
10 0 0 0001
15 1 0 0010
20 0 0 0010
25 1 0 0011
30 0 0 0011
35 1 0 0100
40 0 0 0100
45 1 0 0101
50 0 0 0101
55 1 0 0110
60 0 0 0110
65 1 0 0111
70 0 1 0111
75 1 0 1000
80 0 0 1000
85 1 0 1001
90 0 0 1001
95 1 0 1010
100 0 0 1010
105 1 0 1011
107 1 1 1011
110 0 1 1011
115 1 1 0000
Stopped at time : 120 ns

Transcript 15: Binary Synchronous Reset 4bit Counter

PART-A: NON-INTERFACING 40 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

16. Binary Asynchronous Reset 4bit Counter

Binary Asynchronous Reset 4

rst bin_out
4bit Counter outputs
inputs

clk
Figure 16: Block Diagram of Binary Asynchronous Reset 4bit Counter

Verilog File Name: bin_counter_async_4bit.v

// Binary asynchronous reset 4bit counter
module bin_async_4bit ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'b0000;
end

always @(posedge clk or posedge rst)

if(rst)
count = 4'b0000;
else
count = count + 4'b0001;
endmodule

Verilog Testbench File Name: bin_counter_async_4bit_test.v

`timescale 1ns/1ps
module count4bit_tb;
reg rst, clk;
wire [3:0] count;

bin_async_4bit uut ( .rst(rst), .clk(clk), .count(count));

initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

PART-A: NON-INTERFACING 41 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

initial
begin
#5; rst=0;
#55;
#10; rst=1;
#5; rst=0;
#30;
#2; rst=1;
#10;
end
initial #120 $finish;
initial $monitor ($time,” %b %b %b ”,clk,rst,count);

endmodule

Waveform 16: Binary Asynchronous Reset 4bit Counter

0 0 1 0000
5 1 0 0001
10 0 0 0001
15 1 0 0010
20 0 0 0010
25 1 0 0011
30 0 0 0011
35 1 0 0100
40 0 0 0100
45 1 0 0101
50 0 0 0101
55 1 0 0110
60 0 0 0110
65 1 0 0111
70 0 1 0000
75 1 0 0001
80 0 0 0001
85 1 0 0010
90 0 0 0010
95 1 0 0011
100 0 0 0011
105 1 0 0100
107 1 1 0000
110 0 1 0000
115 1 1 0000
Stopped at time : 120 ns
Transcript 16: Binary Asynchronous Reset 4bit Counter

PART-A: NON-INTERFACING 42 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
17. BCD Synchronous Reset 4bit Counter

BCD Synchronous Reset 4

rst bcd_out
4bit Counter outputs
inputs

clk
Figure 17: Block Diagram of BCD Synchronous Reset 4bit Counter

Verilog File Name: bcd_counter_sync_4bit.v

// BCD synchronous reset 4bit counter
module bcd_sync ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end
always @(posedge clk)
if(rst)
count = 4'd0;
else if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule

Verilog Testbench File Name: bcd_counter_sync_4bit_test.v

`timescale 1ns/1ps
module count4bit_tb;
reg rst, clk;
wire [3:0] count;

bcd_sync uut ( .rst(rst), .clk(clk), .count(count));

initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

initial
begin
#5; rst=0;
#105;
#10; rst=1;
#15; rst=0;
#30;

PART-A: NON-INTERFACING 43 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
#2; rst=1;
#10;
end
initial #180 $finish;
initial $monitor ($time,” %b %b %b ”,clk,rst,count);

endmodule

Waveform 17: BCD Synchronous Reset 4bit Counter

0 0 1 0000
5 1 0 0001
10 0 0 0001
15 1 0 0010
20 0 0 0010
25 1 0 0011
30 0 0 0011
35 1 0 0100
40 0 0 0100
45 1 0 0101
50 0 0 0101
55 1 0 0110
60 0 0 0110
65 1 0 0111
70 0 0 0111
75 1 0 1000
80 0 0 1000
85 1 0 1001
90 0 0 1001
95 1 0 0000
100 0 0 0000
105 1 0 0001
110 0 0 0001
115 1 0 0010
120 0 1 0010
125 1 1 0000
130 0 1 0000
135 1 0 0001
140 0 0 0001
145 1 0 0010
150 0 0 0010
155 1 0 0011
160 0 0 0011
165 1 0 0100
167 1 1 0100
170 0 1 0100
175 1 1 0000
Stopped at time : 180 ns
Transcript 17: BCD Synchronous Reset 4bit Counter

PART-A: NON-INTERFACING 44 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
18. BCD Asynchronous Reset 4bit Counter

BCD Asynchronous Reset 4

rst bcd_out
4bit Counter outputs
inputs

clk
Figure 18: Block Diagram of BCD Asynchronous Reset 4bit Counter

Verilog File Name: bcd_counter_async_4bit.v

// BCD asynchronous reset 4bit counter
module bcd_async ( rst, clk, count);
input rst,clk;
output [3:0] count;
reg [3:0] count;
initial
begin
count = 4'd0;
end

always @(posedge clk or posedge rst)

if(rst)
count = 4'd0;
else if(count < 4'd9 )
count = count + 4'd1;
else
count = 4'd0;
endmodule

Verilog Testbench File Name: bcd_counter_async_4bit_test.v

`timescale 1ns/1ps
module count4bit_tb;
reg rst, clk;
wire [3:0] count;

bcd_async uut ( .rst(rst), .clk(clk), .count(count));

initial
begin
clk = 0; rst=1;
end
always
#5 clk=~clk;

PART-A: NON-INTERFACING 45 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

initial
begin
#5; rst=0;
#105;
#10; rst=1;
#15; rst=0;
#30;
#2; rst=1;
#10;
end
initial #180 $finish;
initial $monitor ($time,” %b %b %b ”,clk,rst,count);

endmodule

Waveform 18: BCD Asynchronous Reset 4bit Counter

0 0 1 0000
5 1 0 0001
10 0 0 0001
15 1 0 0010
20 0 0 0010
25 1 0 0011
30 0 0 0011
35 1 0 0100
40 0 0 0100
45 1 0 0101
50 0 0 0101
55 1 0 0110
60 0 0 0110
65 1 0 0111
70 0 0 0111
75 1 0 1000
80 0 0 1000
85 1 0 1001
90 0 0 1001
95 1 0 0000
100 0 0 0000
105 1 0 0001
110 0 0 0001
115 1 0 0010
120 0 1 0000
125 1 1 0000
130 0 1 0000
135 1 0 0001
140 0 0 0001
145 1 0 0010
150 0 0 0010
155 1 0 0011
160 0 0 0011
165 1 0 0100
167 1 1 0000
170 0 1 0000
175 1 1 0000
Stopped at time : 180 ns
Transcript 18: BCD Asynchronous Reset 4bit Counter

PART-A: NON-INTERFACING 46 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
19. Binary Any Sequence up down 4bit Counter
4
d_in
load
Binary Any Sequence 4
updown bin_out
4bit Counter outputs
inputs
rst

clk
Figure 19: Block Diagram of Binary Any Sequence 4bit Counter

Verilog File Name: bin_counter_any_seq_4bit.v

// Binary Any Sequence Up Down Counter
module any_seq_bin ( rst,load, clk,din,updown, count);
input rst,clk,updown,load;
input [3:0] din;
output [3:0] count;
reg [3:0] count;

always @(posedge clk)

if(rst)
count = 4'b0000;
else if(load)
count = din;
else if (updown)
count = count + 4'b0001;
else
count = count - 4'b0001;
endmodule

Verilog Testbench File Name: bin_counter_any_seq_4bit_test.v

`timescale 1ns/1ps
module count4bit_tb;
reg rst, Load, clk, updn;
reg [3:0] din;
wire [3:0] count;

any_seq_bin uut ( .rst(rst), .clk(clk), .Load(Load), .updown(updn),

.din(din), .count(count));

initial
begin
clk = 0; rst=1; Load =0; updn =0;
end
always
#5 clk=~clk;
initial
begin
#5; rst=0; Load =1; din = 5;
#5; Load =0;
#55;
#10; updn =1;
#15; rst=1; din= 8;
#30;
PART-A: NON-INTERFACING 47 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
#2; rst=0;
#55;
#10; updn =0;
#10;
end
initial #220 $finish;
initial $display(“\t\tclk\trst\t|Load\tupdown\t|din - - > count|”);
initial $monitor ($time,” %b %b |%b %b|%b - - > %b| ”,clk, rst,
Load, updn, din, count);

endmodule

Waveform 19: Binary Any Sequence up down 4bit Counter

clk rst |Load updown |din - - > count|
0 0 1 |0 0|xxxx - - > xxxx|
5 1 0 |1 0|0101 - - > 0101|
10 0 0 |0 0|0101 - - > 0101|
15 1 0 |0 0|0101 - - > 0100|
20 0 0 |0 0|0101 - - > 0100|
25 1 0 |0 0|0101 - - > 0011|
30 0 0 |0 0|0101 - - > 0011|
35 1 0 |0 0|0101 - - > 0010|
40 0 0 |0 0|0101 - - > 0010|
45 1 0 |0 0|0101 - - > 0001|
50 0 0 |0 0|0101 - - > 0001|
55 1 0 |0 0|0101 - - > 0000|
60 0 0 |0 0|0101 - - > 0000|
65 1 0 |0 0|0101 - - > 1111|
70 0 0 |0 0|0101 - - > 1111|
75 1 0 |0 1|0101 - - > 0000|
80 0 0 |0 1|0101 - - > 0000|
85 1 0 |0 1|0101 - - > 0001|
90 0 1 |0 1|1000 - - > 0001|
95 1 1 |0 1|1000 - - > 0000|
100 0 1 |0 1|1000 - - > 0000|
105 1 1 |0 1|1000 - - > 0000|
110 0 1 |0 1|1000 - - > 0000|
115 1 1 |0 1|1000 - - > 0000|
120 0 1 |0 1|1000 - - > 0000|
122 0 0 |0 1|1000 - - > 0000|
125 1 0 |0 1|1000 - - > 0001|
130 0 0 |0 1|1000 - - > 0001|
135 1 0 |0 1|1000 - - > 0010|
140 0 0 |0 1|1000 - - > 0010|
145 1 0 |0 1|1000 - - > 0011|
150 0 0 |0 1|1000 - - > 0011|
155 1 0 |0 1|1000 - - > 0100|
160 0 0 |0 1|1000 - - > 0100|
165 1 0 |0 1|1000 - - > 0101|
170 0 0 |0 1|1000 - - > 0101|
175 1 0 |0 1|1000 - - > 0110|
180 0 0 |0 1|1000 - - > 0110|
185 1 0 |0 1|1000 - - > 0111|
187 1 0 |0 0|1000 - - > 0111|
190 0 0 |0 0|1000 - - > 0111|
195 1 0 |0 0|1000 - - > 0110|
200 0 0 |0 0|1000 - - > 0110|
205 1 0 |0 0|1000 - - > 0101|
210 0 0 |0 0|1000 - - > 0101|
215 1 0 |0 0|1000 - - > 0100|
Stopped at time : 220 ns
Transcript 19: Binary Any Sequence up down 4bit Counter

PART-A: NON-INTERFACING 48 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
1. 7 Segment to Accept Hex Keypad
7 Segment

PC JT AG (Comman Cathode)

Power CPLD 0 1 2 3
J7 BUS/STRIP CABLE
J1
Supply XC9572
4 5 6 7
J6 BUS/STRIP CABLE
J2 8 9 A B
C D E F
Keypad
CPLD Board Mega KBDSP1
Figure 1: Interface Diagram of CPLD Board and MEGA KBDSP1
4
4 key_sc
key_rl outputs
7 Segment Display
inputs to accept Hex 6
digit
clk Keypad Input Data 7
seg_out

Figure 2: Block diagram of 7Segment Display to accept Hex Keypad Input Data

PART-B: INTERFACING 49 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog File Name: keypad_led_display.v
`timescale 1ns / 1ps

module seg7hexkey( clk, key_rl, key_sc, digit, seg_out );

input clk;
input [3:0] key_rl;
output [3:0] key_sc;
output [5:0] digit;
output [6:0] seg_out;

reg [3:0] key_sc;

reg [6:0] seg_out;

reg [12:0] clk_div =13'b0;

reg [3:0] key_sc_temp = 4'b0001;

assign digit = 6'b111110;

always @(posedge clk)

begin
clk_div = clk_div + 15'b1;
end

always@(posedge clk_div[12])
begin
key_sc_temp = {key_sc_temp[2:0],key_sc_temp[3]};
key_sc = key_sc_temp;
end

always@(posedge clk_div[12])// or posedge key_rl[0] or posedge key_rl[1] or posedge key_rl[2] or

posedge key_rl [3] or key_sc_temp )
begin
// gfedcba
if (key_sc_temp == 4'b0001 && key_rl == 4'b0001) seg_out = 7'b0111111; // 0
else if (key_sc_temp == 4'b0001 && key_rl == 4'b0010) seg_out = 7'b0000110; // 1
else if (key_sc_temp == 4'b0001 && key_rl == 4'b0100) seg_out = 7'b1011011; // 2
PART-B: INTERFACING 50 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
else if (key_sc_temp == 4'b0001 && key_rl == 4'b1000) seg_out = 7'b1001111; // 3
else if (key_sc_temp == 4'b0010 && key_rl == 4'b0001) seg_out = 7'b1100110; // 4
else if (key_sc_temp == 4'b0010 && key_rl == 4'b0010) seg_out = 7'b1101101; // 5
else if (key_sc_temp == 4'b0010 && key_rl == 4'b0100) seg_out = 7'b1111101; // 6
else if (key_sc_temp == 4'b0010 && key_rl == 4'b1000) seg_out = 7'b0000111; // 7
else if (key_sc_temp == 4'b0100 && key_rl == 4'b0001) seg_out = 7'b1111111; // 8
else if (key_sc_temp == 4'b0100 && key_rl == 4'b0010) seg_out = 7'b1101111; // 9
else if (key_sc_temp == 4'b0100 && key_rl == 4'b0100) seg_out = 7'b1110111; // A
else if (key_sc_temp == 4'b0100 && key_rl == 4'b1000) seg_out = 7'b1111100; // b
else if (key_sc_temp == 4'b1000 && key_rl == 4'b0001) seg_out = 7'b0111001; // C
else if (key_sc_temp == 4'b1000 && key_rl == 4'b0010) seg_out = 7'b1011110; // D
else if (key_sc_temp == 4'b1000 && key_rl == 4'b0100) seg_out = 7'b1111001; // E
else if (key_sc_temp == 4'b1000 && key_rl == 4'b1000) seg_out = 7'b1110001; // F
end
endmodule

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5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

UCF File Name (CPLD): keypad_led_display.ucf

#keypad_led_display.ucf
NET "clk" LOC = "p9" ;
NET "digit<0>" LOC = "p68" ;
NET "digit<1>" LOC = "p67" ;
NET "digit<2>" LOC = "p66" ;
NET "digit<3>" LOC = "p65" ;
NET "digit<4>" LOC = "p63" ;
NET "digit<5>" LOC = "p62" ;
NET "key_rl<0>" LOC = "p1" ;
NET "key_rl<1>" LOC = "p84" ;
NET "key_rl<2>" LOC = "p83" ;
NET "key_rl<3>" LOC = "p82" ;
NET "key_sc<0>" LOC = "p5" ;
NET "key_sc<1>" LOC = "p4" ;
NET "key_sc<2>" LOC = "p3" ;
NET "key_sc<3>" LOC = "p2" ;
NET "seg_out<0>" LOC = "p81" ;
NET "seg_out<1>" LOC = "p80" ;
NET "seg_out<2>" LOC = "p79" ;
NET "seg_out<3>" LOC = "p75" ;
NET "seg_out<4>" LOC = "p72" ;
NET "seg_out<5>" LOC = "p71" ;
NET "seg_out<6>" LOC = "p70" ;

PART-B: INTERFACING 52 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
2. LCD Message Display
LCD Display

ELECTRONICS!
PC JTAG

Power CPLD 0 1 2 3
J6 BUS/STRIP CABLE
J2
Supply XC9572
4 5 6 7
8 9 A B
C D E F
Keypad
CPLD Board Mega KBDSP1
Figure 3: Interface Diagram of CPLD Board and MEGA KBDSP1
8
data
input outputs
reg_sel
clk LCD
rd-wr
en

Figure 4: Block Diagram of LCD

PART-B: INTERFACING 53 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog File Name: lcd_message.v

// lcd_message.v
// LCD_message – Behavioral
module lcdmsg (clk, lcd_rs, lcd_rw, lcd_e, lcd_0, lcd_1, lcd_2, lcd_3, lcd_4, lcd_5, lcd_6, lcd_7);
input clk; // synthesis attribute PERIOD clk "4 MHz"
output reg lcd_rs;
output reg lcd_rw;
output reg lcd_7;
output reg lcd_6;
output reg lcd_5;
output reg lcd_4;
output reg lcd_3;
output reg lcd_2;
output reg lcd_1;
output reg lcd_0;
output reg lcd_e;
parameter k = 18;
reg [k+8-1:0] count=0;
reg lcd_busy=1;
reg lcd_stb;
reg [5:0] lcd_code;
reg [6:0] lcd_stuff;

always @ (posedge clk) begin

count <= count + 1;
case (count[k+7:k+2])
0: lcd_code <= 6'h03; // power-on initialization
1: lcd_code <= 6'h03;
2: lcd_code <= 6'h03;
3: lcd_code <= 6'h02;
4: lcd_code <= 6'h02; // function set
5: lcd_code <= 6'h08;
6: lcd_code <= 6'h00; // entry mode set
7: lcd_code <= 6'h06;
8: lcd_code <= 6'h00; // display on/off control
9: lcd_code <= 6'h0C;
PART-B: INTERFACING 54 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
10: lcd_code <= 6'h00; // display clear
11: lcd_code <= 6'h01;
12: lcd_code <= 6'h24; // E
13: lcd_code <= 6'h25;
14: lcd_code <= 6'h24; // L
15: lcd_code <= 6'h2C;
16: lcd_code <= 6'h24; // E
17: lcd_code <= 6'h25;
18: lcd_code <= 6'h24; // C
19: lcd_code <= 6'h23;
20: lcd_code <= 6'h25; // T
21: lcd_code <= 6'h24;
22: lcd_code <= 6'h25; // R
23: lcd_code <= 6'h22;
24: lcd_code <= 6'h24; // O
25: lcd_code <= 6'h2F;
26: lcd_code <= 6'h24; // N
27: lcd_code <= 6'h2E;
28: lcd_code <= 6'h24; // I
29: lcd_code <= 6'h29;
30: lcd_code <= 6'h24; // C
31: lcd_code <= 6'h23;
32: lcd_code <= 6'h25; // S
33: lcd_code <= 6'h23;
34: lcd_code <= 6'h22; // !
35: lcd_code <= 6'h21;
default: lcd_code <= 6'h10;
endcase
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
{lcd_3,lcd_2,lcd_1,lcd_0} <= 4'b1111;
end
endmodule

PART-B: INTERFACING 55 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

UCF File Name (CPLD): LCD_message.ucf

#LCD_message.ucf
NET "clk" LOC = "p9" ;
NET "data<0>" LOC = "p81" ;
NET "data<1>" LOC = "p80" ;
NET "data<2>" LOC = "p79" ;
NET "data<3>" LOC = "p75" ;
NET "data<4>" LOC = "p72" ;
NET "data<5>" LOC = "p71" ;
NET "data<6>" LOC = "p70" ;
NET "data<7>" LOC = "P69" ;
NET "en" LOC = "p66" ;
NET "rd_wr" LOC = "p67" ;
NET "reg_sel" LOC = "p68" ;

PART-B: INTERFACING 56 RCVK

 5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
3. Stepper Motor Speed and Direction Control
KEY
1

Direction
Control
To
J4 Stepper
Motor

PC JTAG

Power CPLD
J6 BUS/STRIP CABLE
J3 KEY1 KEY2 KEY3 KEY4
Supply XC9572

RELAY1 RELAY2

CPLD Board Stepper/DC Motor

Interface Card
Figure 5: Interface Diagram of CPLD Board and Stepper Motor Interface Card

KEY
1
C_A
Direction 4
Control inputs STEPPER MOTOR d_out
clk_4M outputs

Figure 6: Block Diagram of Stepper Motor

PART-B: INTERFACING 57 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog File Name: stepper_motor.v
// stepper_motor.v
// stepper_motor – Behavioral
`timescale 1ns / 1ps
module stepper(clk_4M, C_A, d_out);
input clk_4M, C_A;
output [3:0] d_out;
reg [3:0] d_out;
reg [19:0] clk_div = 20'd0;
integer a ;
reg [3:0] step_d [0:3];

initial
begin
a = 0;
step_d [0]=4'b0110;
step_d [1]=4'b1010;
step_d [2]=4'b1001;
step_d [3]=4'b0101;
end

always@ (posedge clk_4M)

begin
clk_div = clk_div + 1'b1;
end

always@(posedge clk_div[16])
begin
if (C_A)
begin
a=(a==4)?0:(a+1);
end
else
begin
a=(a==0)?3:(a-1);
end
d_out = step_d[a];
PART-B: INTERFACING 58 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

end

endmodule

UCF File Name (CPLD): stepper_motor.ucf

#stepper_motor.ucf
NET "C_A" LOC = "p79" ;
NET "clk_4M" LOC = "p9" ;
NET "d_out<0>" LOC = "p3" ;
NET "d_out<1>" LOC = "p2" ;
NET "d_out<2>" LOC = "p1" ;
NET "d_out<3>" LOC = "p84" ;

PART-B: INTERFACING 59 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
4. DC Motor Speed and Direction Control

PC JTAG

Power CPLD
J6 BUS/STRIP CABLE
J3 KEY1 KEY2 KEY3 KEY4
Supply XC9572

RELAY1 RELAY2
To
J5 DC
Motor

CPLD Board Stepper/DC Motor

Interface Card
Figure 7: Interface Diagram of CPLD Board and DC Motor Interface Card

4
spd_cnt cl
inputs DC MOTOR outputs

clk_4M
acl

Figure 8: Block Diagram of DC Motor

PART-B: INTERFACING 60 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog File Name: dcmotor.v

// dcmotor.v
// DC motor – Behavioral

`timescale 1ns / 1ps

module dcmotor(spd_cnt, clk_4M, cl, acl);

input [3:0] spd_cnt;
input clk_4M;
output cl, acl;
reg cl, acl;
reg [20:0] clk_div = 21'd0;

always@ (posedge clk_4M)

begin
clk_div = clk_div + 1'b1;
end

always@(posedge clk_div[19])
begin
case(spd_cnt)
4'b1000 : begin cl = (clk_div[18] && clk_div[15]); acl = 0; end
4'b0100 : begin cl = (clk_div[18] && clk_div[16]); acl = 0; end
4'b0010 : begin cl = (clk_div[19] && clk_div[18]); acl = 0; end
4'b0001 : begin cl = 1; acl = 0; end
4'b0000 : begin cl = 0; acl = 1; end
default : ;
endcase
end

endmodule

PART-B: INTERFACING 61 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

UCF File Name (CPLD): DCmotor.ucf

#DCmotor.ucf
NET "clk_4M" LOC = "p9" ;
NET "spd_cnt<0>" LOC = "p79" ;
NET "spd_cnt<1>" LOC = "p75" ;
NET "spd_cnt<2>" LOC = "p72" ;
NET "spd_cnt<3>" LOC = "p71" ;
NET "cl" LOC = "p5" ;
NET "acl" LOC = "p4" ;

PART-B: INTERFACING 62 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
5. Signal Generator Using DAC
J5
To
CRO

PC JTAG

Power CPLD
J6 BUS/STRIP CABLE
J2 RELAY3 RELAY1
Supply XC9572

RELAY4 RELAY2

CPLD Board DAC/Relay

Interface Card
Figure 9: Interface Diagram of CPLD Board and DAC Interface Card

rst

inputs
Signal Generator 8
dac_out
using DAC
clk outputs

Figure 10: Block Diagram of Sine/Triangular/Square/Ramp Wave Generator using DAC

The DAC interface consists of 8 bit Digital to Analog Converter (DAC 0800). The outputs of which
are converted to Voltages using OPAMP (LM324). The Voltage Outputs terminated at J6 (Vout) and
corresponding 4mA-20mA at J7 Connector

PART-B: INTERFACING 63 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog File Name: DAC_Sine.v
// DAC_Sine.v V
// DAC_Sine – Behavioral

`timescale 1ns / 1ps

module dac_sine(dac_out, clk, rst);
output [7:0] dac_out;
input clk, rst;
reg [7:0] dac_out;
reg [7:0] sine [0:31
integer i; 0 t
initial begin
i = 0;
sine[0]=128;
sine[1]=153;
sine[2]=177;
sine[3]=199;
sine[4]=219;
sine[5]=234;
sine[6]=246; (θ=2,4,6,……) degree of sine using the equation
sine[7]=254;
V=5V +5V Sinθ
sine[8]=255;
sine[9]=254; Eg: θ=0
sine[10]=246;
sine[11]=234; 1. V=5V +5V Sin θ = 5V
sine[12]=219; 2. Resolution of the DAC: 8-bit (2pow8=256) Steps
sine[13]=199;
V:10V(p.p)→ Full Scale Voltages
sine[14]=177;
sine[15]=153; So, 256 Steps/10V = 25.6 Steps per Volt.
sine[16]=128; The Value Sent to DAC is
sine[17]=103; (25.6 * 5)V=128.
sine[18]=79;
sine[19]=57;
sine[20]=37;
sine[21]=22;
sine[22]=10;
PART-B: INTERFACING 64 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
sine[23]=2;
sine[24]=0;
sine[25]=2;
sine[26]=10;
sine[27]=22;
sine[28]=37;
sine[29]=57;
sine[30]=79;
sine[31]=103;
end

always@(posedge (clk))

begin
if(rst)
dac_out = 8'b0;
else
begin
dac_out = sine[i];
i = i + 1;
if (i == 31)
i = 4;
end
end
endmodule

PART-B: INTERFACING 65 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

UCF File Name (CPLD): DAC_Sine.ucf

#DAC_Sine.ucf
NET "clk" LOC = "p9" ;
NET "rst" LOC = "p12" ;
NET "dac_out<0>" LOC = "p81" ;
NET "dac_out<1>" LOC = "p80" ;
NET "dac_out<2>" LOC = "p79" ;
NET "dac_out<3>" LOC = "p75" ;
NET "dac_out<4>" LOC = "p72" ;
NET "dac_out<5>" LOC = "p71" ;
NET "dac_out<6>" LOC = "p70" ;
NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING 66 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
Verilog File Name: DAC_Square.v
// DAC_Square.v
// DAC_Square – Behavioral V
`timescale 1ns / 1ps

module dac_sq(dac_out, clk, rst);

output [7:0] dac_out;
input clk, rst;
reg [7:0] dac_out;
reg [7:0] count;

always@(posedge clk)
begin
if(rst) 0
count <= 8'b0; t
else
count <= count +1'b1;
if (count[7]== 1'b1)
dac_out <= 8'b00000000;
else
dac_out <= 8'b11111111;
end

endmodule

PART-B: INTERFACING 67 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

UCF File Name (CPLD): DAC_Square.ucf

#DAC_Square.ucf
NET "clk" LOC = "p9" ;
NET "rst" LOC = "p12" ;
NET "dac_out<0>" LOC = "p81" ;
NET "dac_out<1>" LOC = "p80" ;
NET "dac_out<2>" LOC = "p79" ;
NET "dac_out<3>" LOC = "p75" ;
NET "dac_out<4>" LOC = "p72" ;
NET "dac_out<5>" LOC = "p71" ;
NET "dac_out<6>" LOC = "p70" ;
NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING 68 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog File Name: DAC_Triangular.v

// DAC_Triangular.v V
// DAC_Triangular – Behavioral

`timescale 1ns / 1ps

module dac_triangle(dac_out, clk, rst);

output [7:0] dac_out;
input clk, rst;
reg [7:0] dac_out;

reg downup;

always@(posedge clk) 0 t
begin
if(rst)
begin
downup <= 1'b0;
dac_out <= 8'b0;
end
else
begin
if (dac_out == 8'b0)
begin
downup <= 1'b0;
dac_out <= 8'b00000001;
end
else if (dac_out == 8'b11111111)
begin
downup <= 1'b1;
dac_out <= 8'b11111110;
end
else if (downup)
dac_out <= dac_out - 1;
else
dac_out <= dac_out +1;
PART-B: INTERFACING 69 RCVK
5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru
end
end
endmodule

UCF File Name (CPLD): DAC_Triangular.ucf

#DAC_Triangular.ucf
NET "clk" LOC = "p9" ;
NET "rst" LOC = "p12" ;
NET "dac_out<0>" LOC = "p81" ;
NET "dac_out<1>" LOC = "p80" ;
NET "dac_out<2>" LOC = "p79" ;
NET "dac_out<3>" LOC = "p75" ;
NET "dac_out<4>" LOC = "p72" ;
NET "dac_out<5>" LOC = "p71" ;
NET "dac_out<6>" LOC = "p70" ;
NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING 70 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog File Name: DAC_Pos_Ramp.v

// DAC_Pos_Ramp.v V
// DAC_Pos_Ramp - Behavioral
`timescale 1ns / 1ps

module dac_posramp(dac_out, clk, rst);

output [7:0] dac_out;
input clk, rst;
reg [7:0] dac_out;

always@(posedge clk)
begin
if(rst) 0 t
dac_out <= 8'b0;
else
dac_out <= dac_out - 1;
end

endmodule

UCF File Name (CPLD): DAC_Pos_Ramp.ucf

#DAC_Pos_Ramp.ucf
NET "clk" LOC = "p9" ;
NET "rst" LOC = "p12" ;
NET "dac_out<0>" LOC = "p81" ;
NET "dac_out<1>" LOC = "p80" ;
NET "dac_out<2>" LOC = "p79" ;
NET "dac_out<3>" LOC = "p75" ;
NET "dac_out<4>" LOC = "p72" ;
NET "dac_out<5>" LOC = "p71" ;
NET "dac_out<6>" LOC = "p70" ;
NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING 71 RCVK

5TH SEM, HDL Lab, 17ECL58 2019-20 DEPT. E&C, CEC, Bengaluru

Verilog File Name: DAC_Neg_Ramp.v

// DAC_Neg_Ramp.v V
// DAC_Neg_Ramp – Behavioral

`timescale 1ns / 1ps

module dac_negramp(dac_out, clk, rst);

output [7:0] dac_out;
input clk, rst;
reg [7:0] dac_out;
always@(posedge clk)
begin
if(rst)
dac_out <= 8'b0;
0 t
else
dac_out <= dac_out + 1;
end
endmodule

UCF File Name (CPLD): DAC_Neg_Ramp.ucf

#DAC_Neg_Ramp.ucf
NET "clk" LOC = "p9" ;
NET "rst" LOC = "p12" ;
NET "dac_out<0>" LOC = "p81" ;
NET "dac_out<1>" LOC = "p80" ;
NET "dac_out<2>" LOC = "p79" ;
NET "dac_out<3>" LOC = "p75" ;
NET "dac_out<4>" LOC = "p72" ;
NET "dac_out<5>" LOC = "p71" ;
NET "dac_out<6>" LOC = "p70" ;
NET "dac_out<7>" LOC = "p69" ;

PART-B: INTERFACING 72 RCVK