Title

Experiments with Signals and Systems, Laplace Transform, Z-Transform and Fourier Transform.
Abstract
The edaplayground was used to better understand the concepts of VHDL code. This also gave
the opportunity to learn to write several programs with the VHDL codes to design and
implement the digital circuits using the edaplayground platform.
Introduction
A digital circuit is a circuit where the signal must be one of two discrete levels. Each level is
interpreted as one of two different states (for example, on/off, 0/1, true/false). Digital circuits use
transistors to create logic gates in order to perform Boolean logic. These cicuits are designed
using VHDL code. VDHL code is a hardware description language (HDL) that can model the
behavior and structure of digital systems at multiple levels of abstraction, ranging from the
system level down to that of logic gates, for design entry, documentation, and verification
purposes.
The purpose of the study is to:
 To become familiar with VHDL programming.
 To write VHDL code for implementing Digital Circuits.
 To compile and simulate VHDL code using Aldec Riviera Pro VHDL Simulator on the
EDA playground website.
Materials and method
The materials used in this experiment was a computer with the edaplayground website. The
specific. To run the simulation, the Aldec Riviera Pro VHDL Simulator was used. This was used
to:
 Type the requested VHDL code
 Implement a design and testbench code
 Run the code
 Simulate the code
Results
Half adder:
Design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity halfadder is
Port(A,B : in std_logic;
Sum,Cout: out std_logic);
end halfadder;

architecture myHalfAdder of halfadder is

Begin
Sum <= A xor B;
Cout<= A and B;
end myHalfAdder;

Full adder
Design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY fulladder IS
PORT (A, B, Cin : IN std_logic;
Sum, Cout : OUT std_logic);
END fulladder;
ARCHITECTURE myfulladd OF fulladder IS
signal Sum_sig,Cout1_sig,Cout2_sig:std_logic;

Component halfAdder
port (A,B:in std_logic;
Sum,Cout:out std_logic);
end component;

BEGIN
HA1: halfAdder port map(A,B,Sum_sig, Cout1_sig);
HA2: halfAdder port map(Sum_sig,Cin,Sum,Cout2_sig);
Cout <= Cout1_sig or Cout2_sig;
END myfulladd;

4 bit adder:
Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_fulladder_4bit IS
END tb_fulladder_4bit;

ARCHITECTURE behavior OF tb_fulladder_4bit IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fulladder_4bit
PORT(
 A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Sum : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';

--Outputs
signal Sum : std_logic_vector(3 downto 0);
signal Cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fulladder_4bit PORT MAP (
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
 -- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0001";
B <= "0100";
Cin <= '0';

wait for 100 ns;

A <= "0001";
B <= "0100";
Cin <= '1';

wait for 100 ns;

A <= "0011";
B <= "0111";
Cin <= '0';

wait for 100 ns;

A <= "0011";
B <= "0111";
Cin <= '1';

wait for 100 ns;

A <= "0101";
B <= "0100";
Cin <= '0';
 wait for 100 ns;
A <= "0101";
B <= "0100";
Cin <= '1';

wait for 100 ns;

A <= "1101";
B <= "0100";
Cin <= '0';

wait for 100 ns;

A <= "1101";
B <= "0100";
Cin <= '1';

wait for 100 ns;

A <= "1001";
B <= "0101";
Cin <= '0';

wait for 100 ns;

A <= "1001";
B <= "0101";
Cin <= '1';

wait;
 end process;

END;

Design:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder_4bit is
port(A, B: in std_logic_vector(3 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(3 downto 0);
Cout: out std_logic);
end fulladder_4bit;

architecture hierarchical of fulladder_4bit is

component full_adder
port (A, B, Cin: in std_logic;
Sum, Cout: out std_logic);
end component;
signal sig_c0, sig_c1, sig_c2: std_logic;

begin
FA0 : full_adder port map(A(0), B(0), Cin, Sum(0), sig_c0);
FA1 : full_adder port map(A(1), B(1), sig_c0, Sum(1), sig_c1);
FA2 : full_adder port map(A(2), B(2), sig_c1, Sum(2), sig_c2);
FA3 : full_adder port map(A(3), B(3), sig_c2, Sum(3), Cout);
end hierarchical;
Figure 3 showing the waveform of the 4 bit adder

4 bit adder/subtractor
Testbench:
-- Code your testbench here
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_fourbitaddsub IS
END tb_fourbitaddsub;

ARCHITECTURE behavior OF tb_fourbitaddsub IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fourbitaddsub
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
op : IN std_logic;
Sum : OUT std_logic_vector(3 downto 0);
neg : out std_logic;
 ovf : out std_logic;
Cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal op : std_logic := '0';

--Outputs
signal Sum : std_logic_vector(3 downto 0);
signal Cout : std_logic;
signal neg : std_logic;
signal ovf : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fourbitaddsub PORT MAP (
A => A,
B => B,
op => op,
Sum => Sum,
Cout => Cout,
neg => neg,
ovf => ovf
);
 -- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0101";
B <= "0010";
op <= '0';

wait for 100 ns;

A <= "0101";
B <= "0010";
op <= '1';

wait for 100 ns;

A <= "0010";
B <= "0110";
op <= '0';

wait for 100 ns;

A <= "0010";
B <= "0110";
op <= '1';

wait for 100 ns;

A <= "1101";
B <= "0111";
 op <= '0';

wait for 100 ns;

A <= "1101";
B <= "0111";
op <= '1';

wait;

end process;

END;

Design:
library ieee;

use ieee.std_logic_1164.all;

entity fourbitaddsub is

port(a,b:in std_logic_vector(3 downto 0);

op:in std_logic;
cout, ovf, neg: out std_logic;
s:out std_logic_vector(3 downto 0));

end fourbitaddsub;

architecture structural of fourbitaddsub is

component fulladder_4bit
port(A, B: in std_logic_vector(3 downto 0);
Cin: in std_logic;
Sum: out std_logic_vector(3 downto 0);
Cout: out std_logic);
end component;

signal x,y : std_logic_vector(3 downto 0);

signal z : std_logic_vector(3 downto 0);
begin
z <= b xor op;

FA1: fulladder_4bit port map (A=>a, B=>z, Cin=>op, Sum => s, Cout => cout);

ovf <= '1' when (Cout = ‘1’) else '0';

neg <= '1' when (s(3) = op) else '0';
end structural;

Figure 4 showing waveforms of 4 bit adder/subtractor

Discussion
The waveforms that were shown were a result of the written code. The waveforms showed the
periodic change of the inputs over a specific time(100 ns after each input). Due to the
inexperience of the user, the simulated waveforms were not perfect as some of the output
waveforms were missing.
Literature cited
No literature cited.