Introduction to Quartus 9.

1 (Tutorial)

Objective
-Getting familiar in using Quartus 9.1
-To perform waveform simulation on schematic diagram of logic gates

References

1. Donald P.Leach: Experimental in Digital Principles, 3rd Edition

2. Malvino/Leach: Digital Principles and Applications
3. Bartee: Digital Computer Fundamentals, 6th Edition
4. Quartus II Handbook Version 9.1 Volume 1: Design and Synthesis

Software
1. Quartus II 9.1

Introduction
The revolutionary Intel® Quartus® Prime Design Software includes everything you need to design for
Intel® FPGAs, SoCs, and complex programmable logic device (CPLD) from design entry and synthesis
to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-
million logic elements are providing designers with the ideal platform to meet next-generation design
opportunities.

Procedure
Part I- (A) Schematic Drawing
Note: This tutorial assumes students have already installed Quartus version 9.1 in their own computer.
1. Create new project in Quartus II. Click on “Create a New Project” or go to “File > New Project
Wizard”.

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2. In page 1 of 5, choose the location of your working directory and type in the name of your project
as Tutorial (you can rename it to whatever name that you want). Click on “Next”

3. Skip page 2 of 5 by click “Next”.

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4. In page 3 of 5, we must specify the type of device in which the designed circuit will be implemented.
Choose “Cyclone™ II” for device family and “EP2C20F484C7” for available devices. Click “OK”

5. Click on “Next” to skip page 4 of 5.

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6. In page 5 of 5, a summary of the chosen settings appears in the screen. Click “Finish”, which returns
to the main Quartus II window.

7. Select “File > New”, choose “Block Diagram/Schematic File”, and click “OK”. This opens the
Graphic Editor window. The first step is to specify a name for the file that will be created. Select
“File > Save As”. In the box labeled “Save as type” choose “Block Diagram/Schematic File
(*.bdf)”. In the box labeled “File name” enter Tutorial (Compulsary to put the same name as the
project name specified in step 2). Put a checkmark in the box “Add file to current project”. Click
“Save”, which puts the file into the directory Tutorial. You can now start designing the circuit. Save
the file by clicking “File > Save”.

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8. The Graphic Editor provides a number of libraries which include circuit elements that can be
imported into a schematic. Double-click on the blank space in the Graphic Editor window, or click
on the icon in the toolbar that looks like an AND gate. A pop-up box in figure below will appear.
Type in the name of the component in the “Name” box to search the component (Alternatively you
can choose primitives > logic and look for the components there). Click “OK” to place the
component (press ESC if you want to stop removing component)

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9. Construct an AND gate logic gate circuit that have 2 inputs and 1 output. Place an ‘AND2’ logic
gate, two ‘input’ and an ‘output’ as shown in figure below. Rename the pin name to A,B and C by
double clicking the “pin_name”. Connect all the inputs and output using wires as provided (or point
out the cursor on the edge of the component, click and drag to connect). Click on compile (purple
play icon) to start compilation of your schematic (you need to do compilation each time you modify
or edit your schematic). Make sure there are no errors. Typical simulation usually have several
warnings. These are usually negligible.

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Part I- (B) Functional Simulation

1. Open the Waveform Editor window by selecting “File > New”. Click on the
“Verification/Debugging Files” branch. Choose “Vector Waveform File” and click “OK”.

2. Save the file under the name Tutorial.vwf (Compulsory to put the same name as the project name
specified in step 2 of previous section). Set the desired simulation to run from 0 to 10s by selecting
“Edit > End Time” and entering 10s in the dialog box. Selecting “View > Fit in Window”
displays the entire simulation range of 0 to 10s in the window.

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3. Next, we want to include the input and output nodes of the circuit to be simulated. Click “Edit >
Insert > Node or Bus”. It is possible to type the name of a signal (pin) into the Name box, but it
is easier to click on the button labeled “Node Finder”. The Node Finder utility has a filter used to
indicate what type of nodes are to be found. Since we are interested in input and output pins, set
the filter to “Pins: all”. Click the “List” button to find the input and output nodes as indicated on
the left side of the figure. Select all signals and click the “>” sign to add it to the Selected Nodes
box on the right side of the figure. Click “Ok” to close the Node Finder Window and then “Ok”
again. This leaves a fully displayed Waveform Editor window.

4. Select signal A, by selecting the icon, then click signal A. Then click the icon and fill value
of period as 1 second. Do the same from signal B and set the period to 2 seconds. Then save the
file.

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5. Run the Compiler by selecting “Processing > Start Compilation”. When there is no error, run the
simulation by selecting “Processing > Start Simulation”. At the end of the simulation, Quartus
II software indicates its successful completion and displays a Simulation Report. Again, go to
“View > Fit in Window” to display the entire simulation range of 0 to 10s in the window.

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6. Evaluate the timing diagram. You can drag the pointer to any specific location that you want to see
the input and output of the timing diagram.

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For example, in this diagram, when A is 1 and B is 0, the output C is 0. This indicates that A(1) AND
B(0) will equal to C(0). Try to modify the diagram using OR gate, XOR gate etc. and see the waveform
of the output.

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