SIMULACION

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Simulacion is

architecture Behavioral of Simulacion is

component compuerta1

Port ( A: in STD_LOGIC;

B: in STD_LOGIC;

F: out STD_LOGIC;

);

end component;

-- Señales de las entradas

signal A_S, B_S : STD_LOGIC:= '0';

-- Señales de salidas

signal F_S : STD_LOGIC;

begin

UO: compuerta1 Port map (

A=> A_S,

B=> B_S,

F=> F_S,
);

process begin

--- Estímulos de la simulación wait for 100 ns;

A_S <= '0';

B_S <= '0';

wait for 100 ns;

A_S <= '1';

B_S <= '0';

wait for 100 ns;

A_S <= '0';

B_S <= '1';

wait for 100 ns;

A_S <= '1';

B_S <= '1';

wait for 100 ns;

wait;

end process;

end Behavioral;
DISEÑO

--------------------------------------------------------------------------------

-- Nombre: Jose Lui Martinez Rocha

-- Documento: 1101756229

-- Fecha:07/09/2020

-- Proyecto: Diseño simulación de una Compuerta AND

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity compuerta1 is

Port ( A: in STD_LOGIC;

B: in STD_LOGIC;

F: out STD_LOGIC;

);

end compuerta1;

architecture Behavioral of compuerta1 is

begin

-- DISEÑO

F <= A and B;

end Behavioral;