Implemente un contador de 3 a 9, si la salida del contador es

mayor al ltimo digito de tu cdigo de alumno activa la salida.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MODELO05 IS
PORT( CLOCK : IN STD_LOGIC ;
COD : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
MAYOR : OUT STD_LOGIC);
END MODELO05;

ARCHITECTURE RTL OF MODELO05 IS
BEGIN
PROCESS (CLOCK)
VARIABLE COUNT: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF (RISING_EDGE(CLOCK)) THEN
CASE COUNT IS
WHEN "0011"=> COUNT:="0100";
WHEN "0100"=> COUNT:="0101";
WHEN "0101"=> COUNT:="0110";
WHEN "0110"=> COUNT:="0111";
WHEN "0111"=> COUNT:="1000";
WHEN "1000"=> COUNT:="1001";
WHEN "1001"=> COUNT:="0011";
WHEN OTHERS=> COUNT:="0011";
END CASE;

IF (COUNT > COD) THEN
MAYOR <= '1';
END IF;

END IF;
END PROCESS;
END RTL;

Dada la siguiente function:

F(A, B, C, D) = m(1, 13, 14)+ m
x
+ m
y
+ m
z

Donde X, Y y Z son los tres ltimos dgitos de tu cdigo de
alumno, implemente el circuito:
Utilizando los siguientes componentes.


A. MUX 8-1


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY modelo06 IS
PORT(
A : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DOUT : OUT STD_LOGIC);
END modelo06;

ARCHITECTURE RTL OF modelo06 IS
BEGIN

PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN"000"=> DOUT<= '0';
WHEN"001"=> DOUT<= NOT A;
WHEN"010"=> DOUT<= NOT A;
WHEN"011"=> DOUT<= NOT A;
WHEN"100"=> DOUT<= '0';
WHEN"101"=> DOUT<= '1';
WHEN"110"=> DOUT<= A;
WHEN"111"=> DOUT<= '0';
WHEN OTHERS=> DOUT<= 'Z';
END CASE;
END PROCESS;
END RTL;

B. MUX 4-1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY modelo07 IS
PORT(
A, B : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DOUT : OUT STD_LOGIC);
END modelo07;

ARCHITECTURE BEH123 OF modelo07 IS
BEGIN

PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN"00"=> DOUT <= '0';
WHEN"01"=> DOUT <= (NOT A) OR B;
WHEN"10"=> DOUT <= A XOR B;
WHEN"11"=> DOUT <= (NOT A) AND (not b);
WHEN OTHERS=> DOUT <= 'Z';
END CASE;
END PROCESS;
END BEH123;

C. DEC 3-8:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY modelo08 IS
PORT
( inp : IN STD_LOGIC_VECTOR(2 downto 0);
A : IN STD_LOGIC;
X : OUT STD_LOGIC);

END modelo08;

ARCHITECTURE RTL OF modelo08 IS
SIGNAL outp: std_logic_vector(7 downto 0);
BEGIN
outp(0)<= '0' WHEN INP = "000" ELSE '0';
outp(1)<= NOT A WHEN INP = "001" ELSE '0';
outp(2)<= NOT A WHEN INP = "010" ELSE '0';
outp(3)<= NOT A WHEN INP = "011" ELSE '0';
outp(4)<= '0' WHEN INP = "100" ELSE '0';
outp(5)<= '1' WHEN INP = "101" ELSE '0';
outp(6)<= A WHEN INP = "110" ELSE '0';
outp(7)<= '1' WHEN INP = "111" ELSE '0';

X <= outp(0) or outp(1) or outp(2) or outp(3) or outp(4) or outp(5) or outp(6) or
outp(7);

END RTL;

Dado el siguiente circuito conbinacional:




LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PROBLEM3 IS

PORT( A,B,C : IN STD_LOGIC;
D,E: OUT STD_LOGIC);
END PROBLEM3;

ARCHITECTURE BEHAVIOUR OF PROBLEM3 IS
SIGNAL INTER :STD_LOGIC;
SIGNAL INTER1:STD_LOGIC;
SIGNAL INTER2:STD_LOGIC;
SIGNAL INTER3:STD_LOGIC;

BEGIN

INTER<=(A NAND B);
INTER1<=(A NOR B);
INTER2<=(NOT C AND INTER);
INTER3<=(NOT INTER1 AND INTER);
D<= INTER2 NOR INTER1;
E<= INTER3 XOR C;

END BEHAVIOUR;