ESCUELA SUPERIOR POLITECNICA DE CHIMBORAZO

FACULTAD DE INFORMATICA Y ELECTRONICA

ESCUELA DE INGENIERIA EN ELECTRONICA, REDES Y
TELECOMUNICACIONES

MATERIA: SISTEMAS DIGITALES PARALELO: “C”

NOMBRES: Rony Fabricio Basantes Asqui CODIGO: 1015

EJERCICIOS DE PRACTICA CUALESQUIERA

DISENAR UNA COMPUERTA NOR

CODIGO

library ieee;
use ieee.std_logic_1164.all;

entity puertanor is
port (

a,b : in std_logic;

f : out std_logic

);
end puertanor;

architecture rfba of puertanor is

begin

f<= a xnor b;

end rfba;

RTL
CAPTURA DEL CODIGO
2 OPERADOR QUE CUMPLA CON LA FUNCION

CODIGO

library ieee;
use ieee.std_logic_1164.all;

entity opefunc is
port (

A,B,C : IN std_logic;

f : out std_logic

);
end opefunc;

architecture rfba of opefunc is

begin

f<= (not A and B)or(not B and C)or(A and not C);

END RFBA;

RTL
COMENTARIO

Declarar las tres variables en este caso A,B,C y su F

utilizar los operadores como NOT, AND, OR

3 MULTIPLEXOR CON 4 SENALES DE ENTRADA (WITH-SELECT)

library ieee;
use ieee.std_logic_1164.all;

entity muxwithsel is
port(

h : in std_logic_vector(3 downto 0);

s: in std_logic_vector(1 downto 0);

f: out std_logic

);
end muxwithsel;

architecture rfba of muxwithsel is

begin

with s select
f<= h(0) when "00",
h(1) when "01",
h(2) when "10",
h(3) when others ;

end rfba;
4 DECODIFICSADOR DE 3 ENTRADAS 8 SALIDAS (WI5H SELECT)

library ieee;

use ieee.std_logic_1164.all;

entity decowithsel is

port (

A : in std_logic_vector(2 downto 0);

B : out std_logic_vector(7 downto 0)

);

end decowithsel;
architecture rfba of decowithsel is

begin

with A select

b<= "00000001" when "000",

"00000010" when "001",

"00000100" when "010",

"00001000" when "011",

"00010000" when "100",

"00100000" when "101",

"01000000" when "110",

"10000000" when others;

end rfba;
5 SUMADOR SIN ACARREO

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity sum is

port (

a,b: in signed (4 downto 0);

s: out signed (4 downto 0)

);

end sum;

architecture rfba of sum is

begin

s<= a + b;

end rfba;
6 SUMADOR CON ACARREO

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity sumacarreo is

port (

a,b : in std_logic_vector(3 downto 0);

ci : in std_logic;

s : out std_logic_vector(3 downto 0);

co: out std_logic);

end sumacarreo;

architecture rfba of sumacarreo is

signal suma: std_logic_vector(4 downto 0);

BEGIN

suma <= ('0'& A) + B + ci ; S <= suma(3 downto 0);

co <= suma(4);

end rfba;
7 CODIFICADOR 4-2 CON PRIORIDAD

library ieee;

use ieee.std_logic_1164.all;

entity codiprio is

port (

w:in std_logic_vector (3 downto 0);

y: out std_logic_vector (1 downto 0);

z: out std_logic);

end codiprio;

architecture rfba of codiprio is

begin

with w select

y<= "00" when "0001",

"01" when "0010",

"01" when "0011",

"10" when "0100",

"10" when "0101",

"10" when "0110",

"10" when "0111",

"11" when others;

with w select

z<= '0' when "0000",

'1' when others;

end rfba;
Ejemplo 1 en claces

library ieee;

use ieee.std_logic_1164.all;

entity ejemplo1 is

port (A: in std_logic_vector (6 downto 0);

B: in std_logic;

SAL: out std_logic_vector(2 downto 0)

);

end ejemplo1;

architecture rfba of ejemplo1 is

begin

SAL <= "000" when B/='1' else

"000" when A(0) = '1' else

"001" when A(1) = '1' else

"010" when A(2) = '1' else

"011" when A(3) = '1' else

"100" when A(4) = '1' else

"101" when A(5) = '1' else

"110" when A(6) = '1' else

"000";

end rfba;
Ejemplo 2 en claces
Ejemplo 3 en claces

library ieee;

use ieee.std_logic_1164.all;

entity ejemplo3 is

port(

a,b : in std_logic;

y : out std_logic

);

end ejemplo3;

architecture rfba of ejemplo3 is

begin

process (a,b)

begin

y <= a and b;

end process;

end rfba;