Function

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity func is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
f : out STD_LOGIC);
end func;

architecture Behavioral of func is

begin
f <= ((not a) or b or c)and (a or (not b) or (not d)) and (b or (not c) or
(not d)) and (a or b or c or d);
end Behavioral;

TESTBENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY func_testbench IS
END func_testbench;

ARCHITECTURE behavior OF func_testbench IS

COMPONENT func
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
d : IN std_logic;
f : OUT std_logic
);
END COMPONENT;
 --Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';
signal d : std_logic := '0';

--Outputs
signal f : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

--constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: func PORT MAP (
a => a,
b => b,
c => c,
d => d,
f => f
);

-- Clock process definitions

--<clock>_process :process
--begin
--<clock> <= '0';
--wait for <clock>_period/2;
--<clock> <= '1';
--wait for <clock>_period/2;
-- end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

-- wait for <clock>_period*10;

-- insert stimulus here

wait for 10 ns;

a <= '0' ; b <= '0' ; c <= '0'; d <='0';
wait for 10 ns;
a <= '0' ; b <= '0' ; c <= '0'; d <='1';

wait for 10 ns;

a <= '0' ; b <= '0' ; c <= '1'; d <='0';
wait for 10 ns;
 a <= '0' ; b <= '0' ; c <= '1'; d <='1';
wait for 10 ns;
a <= '0' ; b <= '1' ; c <= '0'; d <='0';
wait for 10 ns;
a <= '0' ; b <= '1' ; c <= '0'; d <='1';
wait for 10 ns;
a <= '0' ; b <= '1' ; c <= '1'; d <='0';
wait for 10 ns;
a <= '1' ; b <= '1' ; c <= '1'; d <='1';
wait for 10 ns;
a <= '1' ; b <= '0' ; c <= '0'; d <='0';
wait for 10 ns;
a <= '1' ; b <= '0' ; c <= '0'; d <='1';
wait for 10 ns;
a <= '1' ; b <= '0' ; c <= '1'; d <='0';
wait for 10 ns;
a <= '1' ; b <= '0' ; c <= '1'; d <='1';
wait for 10 ns;
a <= '1' ; b <= '1' ; c <= '0'; d <='0';
wait for 10 ns;
a <= '1' ; b <= '1' ; c <= '0'; d <='1';
wait for 10 ns;
a <= '1' ; b <= '1' ; c <= '1'; d <='0';
wait for 10 ns;
a <= '1' ; b <= '1' ; c <= '1'; d <='1';

wait;
end process;

END;

FULL ADDER
-- -- library IEEE;
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladder1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
s1 : inout STD_LOGIC;
c1 : inout STD_LOGIC;
c2 : inout STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end fulladder1;

architecture Behavioral of fulladder1 is

begin
s1 <= a xor b;
c1 <= a and b;
c2 <= s1 and c;
carry <= c1 or c2;
sum <= s1 xor c;

end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY fulladdertest IS
END fulladdertest;

ARCHITECTURE behavior OF fulladdertest IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fulladder1
PORT(
a : IN std_logic;
b : IN std_logic;
c : IN std_logic;
s1 : INOUT std_logic;
c1 : INOUT std_logic;
c2 : INOUT std_logic;
sum : OUT std_logic;
carry : OUT std_logic
);
END COMPONENT;

--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';
signal c : std_logic := '0';

--BiDirs
signal s1 : std_logic;
signal c1 : std_logic;
signal c2 : std_logic;

--Outputs
 signal sum : std_logic;
signal carry : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fulladder1 PORT MAP (
a => a,
b => b,
c => c,
s1 => s1,
c1 => c1,
c2 => c2,
sum => sum,
carry => carry
);

-- Clock process definitions

-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

-- wait for <clock>_period*10;

-- insert stimulus here

a <='0';b <='0';c <='0';
wait for 100 ns;
a <='0';b <='0';c <='1';
wait for 100 ns;
a <='0';b <='1';c <='0';
wait for 100 ns;
a <='0';b <='1';c <='1';
wait for 100 ns;
a <='1';b <='0';c <='0';
wait for 100 ns;
a <='1';b <='0';c <='1';
wait for 100 ns;
a <='1';b <='1';c <='0';
wait for 100 ns;
a <='1';b <='1';c <='1';
wait for 100 ns;
wait;
end process;

END;

DECODER
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY decoder IS
END decoder;

ARCHITECTURE behavior OF decoder IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT decoder_1
PORT(
e1 : IN std_logic;
e2 : IN std_logic;
e3 : IN std_logic;
a : IN std_logic_vector(2 downto 0);
y : OUT std_logic_vector(0 to 7)
);
END COMPONENT;

--Inputs
signal e1 : std_logic := '0';
signal e2 : std_logic := '0';
signal e3 : std_logic := '0';
signal a : std_logic_vector(2 downto 0) := (others => '0');

--Outputs
signal y : std_logic_vector(0 to 7);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: decoder_1 PORT MAP (
e1 => e1,
e2 => e2,
e3 => e3,
 a => a,
y => y
);

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
e1 <='0'; e2 <='0'; e3 <='0';a <="000";
wait for 10ns;

wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;

END;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY decoder_tb IS
END decoder_tb;

ARCHITECTURE behavior OF decoder_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT decoder_1
PORT(
e1 : IN std_logic;
e2 : IN std_logic;
e3 : IN std_logic;
clk : IN std_logic;
 a : IN std_logic_vector(2 downto 0);
y : OUT std_logic_vector(0 to 7)
);
END COMPONENT;

--Inputs
signal e1 : std_logic := '0';
signal e2 : std_logic := '0';
signal e3 : std_logic := '0';
signal clk : std_logic := '0';
signal a : std_logic_vector(2 downto 0) := (others => '0');

--Outputs
signal y : std_logic_vector(0 to 7);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: decoder_1 PORT MAP (
e1 => e1,
e2 => e2,
e3 => e3,
clk => clk,
a => a,
y => y
);

-- Clock process definitions

clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="UUU";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="000";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="001";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="010";
wait for 10ns;
 e1 <='1'; e2 <='1'; e3 <='1';a <="011";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="100";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="101";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="110";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="111";
wait for 10ns;
e1 <='1'; e2 <='1'; e3 <='1';a <="UUU";
wait for 10ns;

wait for clk_period*10;

-- insert stimulus here

wait;
end process;

END;

COUNTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
Port ( clk,reset : in STD_LOGIC;
digit1,digit2 : out STD_LOGIC_VECTOR(6 DOWNTO 0));
end counter;

architecture behavioral of counter is

begin
process(clk,reset)
variable temp1 : integer range 0 to 10;

variable temp2 : integer range 0 to 10;

begin
if (reset='1') then
temp1:=0;
temp2:=0;
elsif (clk' event and clk='1') then
temp1:= temp1 + 1;
if (temp1=10) then
temp1:=0;
temp2:=temp2+1;
if (temp2=10) then
temp2 := 0;
end if;
end if;
end if;
case temp1 is
when 0=>digit1 <="1111110";
when 1=>digit1 <="0110000";
when 2=>digit1 <="1101101";
when 3=>digit1 <="1111001";
when 4=>digit1 <="0110011";
when 5=>digit1 <="1011011";
when 6=>digit1 <="1011111";
when 7=>digit1 <="1110000";
when 8=>digit1 <="1111111";
when 9=>digit1 <="1111011";
when others=> null;
end case;
case temp2 is
when 0=>digit2 <="1111110";
when 1=>digit2 <="0110000";
when 2=>digit2 <="1101101";
when 3=>digit2 <="1111001";
when 4=>digit2 <="0110011";
when 5=>digit2 <="1011011";
when 6=>digit2 <="1011111";
when 7=>digit2 <="1110000";
when 8=>digit2 <="1111111";
when 9=>digit2 <="1111011";
when others=> null;
end case;
end process;
end behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY counter_tb IS
END counter_tb;

ARCHITECTURE behavior OF counter_tb IS

 -- Component Declaration for the Unit Under Test (UUT)

COMPONENT counter
PORT(
clk : IN std_logic;
reset : IN std_logic;
digit1 : OUT std_logic_vector(6 downto 0);
digit2 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal digit1 : std_logic_vector(6 downto 0);
signal digit2 : std_logic_vector(6 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: counter PORT MAP (
clk => clk,
reset => reset,
digit1 => digit1,
digit2 => digit2
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

wait for 10 ns;
 reset <= '0';
wait for 10 ns;
reset <= '1';

wait;
end process;

END;

COMPARATOR 2 BIT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

--any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comp2bit is
Port ( a : in STD_LOGIC_VECTOR(1 downto 0);
b : in STD_LOGIC_VECTOR(1 downto 0);
clk: in STD_LOGIC;
equal : out STD_LOGIC);
--greater : out STD_LOGIC;
--lesser : out STD_LOGIC

end comp2bit;

architecture Behavioral of comp2bit is

signal a1, a0, b1, b0,temp1,temp2: std_logic ;

begin
process(clk)
begin
if(clk'event and clk='1') then
a1 <= a(1);
a0 <= a(0);
b1 <= b(1);
b0 <= b(0);
--temp1 <=(a1 and b1) ;
temp2 <= not (b1);
equal <= temp2;
--(not a1) ;
--and (not b1));
--or temp2;
--equal <= ((a0 and b0) or ((not a0) and (not b0))) and ((a1 and b1) or
((not a1) and (not b1)));
--greater <= (a1 and (not b1)) or (((a1 and b1) or ((not a1) and (not
b1))) and (a0 and (not b0)));
--lesser <= ((not a1) and b1) or (((a1 and b1) or ((not a1) and (not b1)))
and ((not a0) and b0));
end if;
end process;
end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY comp2bit_tb IS
END comp2bit_tb;

ARCHITECTURE behavior OF comp2bit_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT comp2bit
PORT(
a : IN std_logic_vector(1 downto 0);
b : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
equal : OUT std_logic);
--greater : OUT std_logic;
--lesser : OUT std_logic

END COMPONENT;

--Inputs
signal a : std_logic_vector(1 downto 0) := (others => '0');
signal b : std_logic_vector(1 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal equal : std_logic;
--signal greater : std_logic;
--signal lesser : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: comp2bit PORT MAP (
a => a,
 b => b,
clk => clk,
equal => equal
);
--greater => greater,
--lesser => lesser

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

-- wait for 100 ns;
-- a <= "00"; b <= "00";
-- wait for 100 ns;
-- a <= "00"; b <= "01";
-- wait for 10 ns;
-- a <= "00"; b <= "10";
-- wait for 10 ns;
-- a <= "00"; b <= "11";
--wait for 10 ns;
a <= "01"; b <= "00";
wait for 100 ns;
a <= "01"; b <= "01";
wait for 100 ns;
a <= "01"; b <= "10";
wait for 100 ns;
a <= "01"; b <= "11";
wait for 100 ns;
-- a <= "10"; b <= "00";
-- wait for 10 ns;
-- a <= "10"; b <= "01";
-- wait for 10 ns;
-- a <= "10"; b <= "10";
-- wait for 10 ns;
-- a <= "10"; b <= "11";
-- wait for 10 ns;
-- a< = "11"; b <= "00";
--wait for 10 ns;
 --a <= "11"; b <= "01";
-- wait for 10 ns;
-- a <= "11"; b <= "10";
-- wait for 10 ns;
-- a <= "11"; b <= "11";
-- wait for 10 ns;
--
-

wait;
end process;

END;

8BITCOMPARATOR
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity comp8bit is
Port ( pass : in STD_LOGIC_VECTOR (7 downto 0);
a : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
right,wrong : out STD_LOGIC);
end comp8bit;

architecture Behavioral of comp8bit is

signal m:std_logic_vector (7 downto 0);

signal equal:std_logic;

begin
process(clk)
begin
if(clk'event and clk='1') then

for i in 0 to 7 loop
m(i) <= (pass(i) and a(i)) or ((not pass(i)) and (not a(i)));

end loop;
equal <= m(0) and m(1) and m(2) and m(3) and m(4) and m(5) and m(6) and
m(7) ;

if(equal = '1') then

right <= '1';

elsif(equal = '0') then

wrong <= '1';
end if;

end if;

end process;

end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY comp8bit_tb IS
END comp8bit_tb;

ARCHITECTURE behavior OF comp8bit_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT comp8bit
PORT(
pass : IN std_logic_vector(7 downto 0);
a : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
right : OUT std_logic;
wrong : OUT std_logic
);
END COMPONENT;

--Inputs
signal pass : std_logic_vector(7 downto 0) := (others => '0');
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal right : std_logic;
signal wrong : std_logic;
 -- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: comp8bit PORT MAP (
pass => pass,
a => a,
clk => clk,
right => right,
wrong => wrong
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

--pass <= "10110011" ; a <= "10110011";
--wait for 100 ns;
pass <= "10110011" ; a <= "11111111";

wait;
end process;

END;

ANDGATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity and_gate is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end and_gate;

architecture Behavioral of and_gate is

begin
z <= x and y;

end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY and_gate2_tb IS
END and_gate2_tb;

ARCHITECTURE behavior OF and_gate2_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT and_gate
PORT(
x : IN std_logic;
y : IN std_logic;
z : OUT std_logic
);
END COMPONENT;

--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';

--Outputs
signal z : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

constant <clock>_period : time := 10 ns;

--BEGIN

-- Instantiate the Unit Under Test (UUT)

-- uut: and_gate PORT MAP (
-- x => x,
-- y => y,
-- z => z
-- );

-- Clock process definitions

-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;

-- Stimulus process
-- stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
x<='0';y<='0';
wait for 10ns;
x<='0';y<='1';
wait for 10ns;
x<='1';y<='0';
wait for 10ns;
x<='1';y<='1';
wait for 10ns;

wait for <clock>_period*10;

-- insert stimulus here

wait;
end process;

END;

PASSWORD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity password is
Port ( password_out : out STD_LOGIC_VECTOR (7 downto 0);
a : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
right,wrong : out STD_LOGIC);
end password;

architecture Behavioral of password is

signal m:std_logic_vector (7 downto 0);
signal equal: std_logic;
signal pass: std_logic_vector (7 downto 0) := "11111111";

begin
process(clk)
begin
if(clk'event and clk='1') then

for i in 0 to 7 loop
m(i) <= (pass(i) and a(i)) or ((not pass(i)) and (not a(i)));

end loop;

equal <= m(0) and m(1) and m(2) and m(3) and m(4) and m(5) and m(6) and
m(7) ;

if (equal = '1') then

right <= '1';
wrong <= '0';

elsif (equal = '0') then

wrong <= '1';
right <= '0';
end if;

end if;
password_out <= pass;

end process;

end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY password_tb IS
END password_tb;

ARCHITECTURE behavior OF password_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT password
PORT(
password_out : OUT std_logic_vector(7 downto 0);
a : IN std_logic_vector(7 downto 0);
clk : IN std_logic;
right : OUT std_logic;
wrong : OUT std_logic
);
END COMPONENT;

--Inputs
signal password_out : std_logic_vector(7 downto 0);
signal a : std_logic_vector(7 downto 0) := (others => '0');
signal clk : std_logic := '0';

--Outputs
signal right : std_logic;
signal wrong : std_logic;
--:= (others => '0');
--signal pass : std_logic_vector( 7 downto 0) ;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: password PORT MAP (
password_out => password_out,
a => a,
clk => clk,
right => right,
wrong => wrong
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
 end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

a <= "10110011";
wait for 100 ns;
a <= "11111111";

wait for 100 ns;

a <= "11110011";

wait for 100 ns;

a <= "10110011";
wait for 100 ns;
a <= "01111010";
wait;
end process;

END;

D FLIPFLOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(clk,rst)
begin
if(rst='1')then
q<='0';
elsif(clk' event and clk='1')then
q<=d;
end if;
end process;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_testbench IS
END dff_testbench;

ARCHITECTURE behavior OF dff_testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT dff
PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic);
END COMPONENT;

--Inputs
signal d : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';

--Outputs
signal q : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: dff PORT MAP (
d => d,
clk => clk,
rst => rst,
 q => q
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

wait for 10 ns;
rst <= '0'; d <= '0';
wait for 10 ns;
rst <= '0'; d <= '1';
wait for 10 ns;
rst <= '1'; d <= '0';
wait for 10 ns;
rst <= '1'; d <= '1';

end process;

END;

INCREMENTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_arith.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity incrementer_1 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
 k : integer;
z : in std_logic_vector(3 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end incrementer_1;

architecture Behavioral of incrementer_1 is

variable k : std_logic_vector(3 downto 0);

begin
process(reset,clk)
begin
if (clk'event and clk='1')then
for(k=0;k<=7;k=k+1)
if(reset==k)then
y(k)='1';
else
y(k) <= 0;
end for;
end if;
end if;

end process;

end Behavioral;

TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY incrementer_tb IS
END incrementer_tb;

ARCHITECTURE behavior OF incrementer_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT incrementer_1
PORT(
reset : IN std_logic;
clk : IN std_logic;
z : std_logic_vector(3 downto 0);
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;

--Inputs
signal reset : std_logic := '0';
 signal clk : std_logic := '0';

--Outputs
signal z : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: incrementer_1 PORT MAP (
reset => reset,
clk => clk,
z => z
);

-- Clock process definitions

clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
z <= "0000";reset <='1';
wait for 100 ns;
z <= "0001";reset <='1';
wait for 100 ns;
z <= "0010";reset <='1';
wait for 100 ns;
z <= "0011";reset <='1';
wait for 100 ns;
z <= "0100";reset <='1';
wait for 100 ns;
z <= "0101";reset <='1';
wait for 100 ns;
z <= "0110";reset <='1';
wait for 100 ns;
z <= "1111";reset <='1';
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

wait;
 end process;

END;