Program 1:

Write VHDL code to display Hexadecimal numbers 0 to F on

selected seven Segment display.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcd_seg is

Port (en1 : out std_logic;

en2 : out std_logic;

en3 : out std_logic;

en4 : out std_logic;

en5 : out std_logic;

en6 : out std_logic;

sel : in std_logic_vector(2 downto 0);

count : in std_logic_vector(3 downto 0);

dis_out:out std_logic_vector(7 downto 0));

end bcd_seg;

architecture Behavioral of bcd_seg is

begin

process (sel)
begin

if sel = "000" then

en1 <='1';

en2 <= '0';

en3 <= '0';

en4 <= '0';

en5 <= '0';

en6 <= '0';

end if;

if sel = "001" then

en1 <= '0';

en2 <= '1';

en3 <= '0';

en4 <= '0';

en5 <= '0';

en6 <= '0';

end if;

if sel = "010" then

en1 <= '0';

en2 <= '0';

en3 <= '1';

en4 <= '0';

en5 <= '0';

en6 <= '0';

 end if;

if sel = "011" then

en1 <= '0';

en2 <= '0';

en3 <= '0';

en4 <= '1';

en5 <= '0';

en6 <= '0';

end if;

if sel = "100" then

en1 <= '0';

en2 <= '0';

en3 <= '0';

en4 <= '0';

en5 <= '1';

en6 <= '0';

end if;

if sel = "101" then

en1 <= '0';

en2 <= '0';

en3 <= '0';

en4 <= '0';

en5 <= '0';

en6 <= '1';

 end if;

end process;

dis_out<= "00000110" when count ="0001" else --1

"01011011" when count= "0010" else --2

"01001111" when count="0011" else --3

"01100110" when count="0100" else --4

"01101101" when count="0101" else --5

"01111101" when count="0110" else --6

"00000111" when count="0111" else --7

"01111111" when count="1000" else --8

"01101111" when count="1001" else --9

"01110111" when count="1010" else --A

"01111100" when count="1011" else --b

"00111001" when count="1100" else --C

"01011110" when count="1101" else --d

"01111001" when count="1110" else --E

"01110001" when count="1111" else --F

"00111111" ; --0

end Behavioral;
Program 2:

Write VHDL code to display message “AMCEC” on an alpha

numeric LCD display.
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is

Port (data : out std_logic_vector(3 downto 0);

cntrl : out std_logic_vector(2 downto 0);

clk : in std_logic);

end lcd;

architecture Behavioral of lcd is

signal clkdiv : std_logic_vector(18 downto 0);

signal clkstate: std_logic_vector(6 downto 0);

signal state32: std_logic_vector(6 downto 0);

signal clkkey : std_logic;

signal lcdheader: std_logic_vector(6 downto 0);

alias lcd_control : std_logic_vector(2 downto 0) is cntrl(2 downto 0);

alias lcd_data : std_logic_vector(3 downto 0) is data(3 downto 0);

begin

P1:process (clk,clkdiv)

begin

if( rising_edge(clk)) then

clkdiv <= clkdiv + 1;

end if;

end process P1;

clkkey <= clkdiv(18);

P2:process (clkkey)

begin

if( rising_edge(clkkey)) then

clkstate <= clkstate + 1;

end if;

end process P2;

state32 <= clkstate;

P3:process (state32,lcdheader)

begin

case state32 is

when "0000000" => lcdheader <= "1000011";--43--init

when "0000001" => lcdheader <= "0000011";--03

when "0000010" => lcdheader <= "1000000";--40--init

when "0000011" => lcdheader <= "0000000";--00

when "0000100" => lcdheader <= "1000010";--42--4bit interface data

when "0000101" => lcdheader <= "0000010";--02

when "0000110" => lcdheader <= "1000010";--42--4bit interface data

when "0000111" => lcdheader <= "0000010";--02

when "0001000" => lcdheader <= "1001000";--48--1line

when "0001001" => lcdheader <= "0001000";--08

when "0001010" => lcdheader <= "1000000";--40

when "0001011" => lcdheader <= "0000000";--00

when "0001100" => lcdheader <= "1000110";--46--incremant

when "0001101" => lcdheader <= "0000110";--06

when "0001110" => lcdheader <= "1000000";--40

when "0001111" => lcdheader <= "0000000";--00

when "0010000" => lcdheader <= "1001111";--4f--wait

when "0010001" => lcdheader <= "0001111";--0f

when "0010010" => lcdheader <= "1000000";--40--clear display

when "0010011" => lcdheader <= "0000000";--00

when "0010100" => lcdheader <= "1000001";--41

when "0010101" => lcdheader <= "0000001";--01

when "0010110" => lcdheader <= "1010100";--54--A

when "0010111" => lcdheader <= "0010100";--14

when "0011000" => lcdheader <= "1010001";--51

when "0011001" => lcdheader <= "0010001";--11

when "0011010" => lcdheader <= "1010100";--54--M

when "0011011" => lcdheader <= "0010100";--14

 when "0011100" => lcdheader <= "1011101";--5D

when "0011101" => lcdheader <= "0011101";--1D

when "0011110" => lcdheader <= "1010100";--54--C

when "0011111" => lcdheader <= "0010100";--14

when "0100000" => lcdheader <= "1010011";--53

when "0100001" => lcdheader <= "0010011";--13

when "0100010" => lcdheader <= "1010100";--54--E

when "0100011" => lcdheader <= "0010100";--14

when "0100100" => lcdheader <= "1010101";--55

when "0100101" => lcdheader <= "0010101";--15

when "0100110" => lcdheader <= "1010100";--54--C

when "0100111" => lcdheader <= "0010100";--14

when "0101000" => lcdheader <= "1010011";--53

when "0101001" => lcdheader <= "0010011";--13

when others => lcdheader <= "1101111";--7ff

end case ;

lcd_data <= lcdheader(3 downto 0);

lcd_control <= lcdheader(6 downto 4);

end process P3;

end Behavioral;
Program 3:

Write VHDL code to control speed and direction of DC motor.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dc_motor is

Port (psw : in std_logic_vector(2 downto 0);

pdcm : out std_logic;

clk : in std_logic);

end dc_motor;

architecture behavioral of dc_motor is

signal cnt : std_logic_vector(7 downto 0):=(others=>'0');

signal sclkdiv : std_logic_vector(11 downto 0):= (others=>'0');

signal clk1: std_logic;

begin

P1:process(clk)

begin

if clk'event and clk ='1' then

cnt <= cnt + 1;

end if;
end process P1;

clk1 <= cnt(7);

P2:process(clk1)

begin

if clk1'event and clk1 ='1' then

if(sclkdiv = "101011110000") then --af0

sclkdiv <= "000000000000";

else

sclkdiv <= sclkdiv+1;

end if;

end if;

end process P2;

P3:process(clk1)

begin

if clk1'event and clk1 = '1' then

if(sclkdiv = "000000000000") then pdcm <= '1';

elsif(psw = "000" and sclkdiv = "000111110100") then pdcm <= '0';

elsif(psw = "001" and sclkdiv = "001100100000") then pdcm <= '0';

elsif(psw = "010" and sclkdiv = "010001001100") then pdcm <= '0';

elsif(psw = "011" and sclkdiv = "010101111000") then pdcm <= '0';

elsif(psw = "100" and sclkdiv = "011010100100") then pdcm <= '0';

elsif(psw = "101" and sclkdiv = "011111010000") then pdcm <= '0';

 elsif(psw = "110" and sclkdiv = "100011111100") then pdcm <= '0';

elsif(psw = "111" and sclkdiv = "100111000100") then pdcm <= '0';

end if;

end if;

end process P3;

end behavioral;
Program 4:

Write VHDL code to control speed and direction of Stepper

motor.
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity stepper_motor is

Port ( clk : in std_logic;

cntrl : in std_logic;

dout : out bit_vector(3 downto 0));

end stepper_motor;

architecture Behavioral of stepper_motor is

signal temp:bit_vector( 3 downto 0):= "0111";

signal clk1: std_logic;

signal cnt : std_logic_vector(20 downto 0):= (others => '0');

begin

P1:process(clk)

begin

if (clk'event and clk ='1') then8

cnt <= cnt + '1';

end if;
end process P1;

clk1 <= cnt(20);

P2:process(clk1)

begin

if clk1'event and clk1 = '1' then

if cntrl = '1' then

temp <= temp rol 1 ; --clockwise rotation

else

temp <= temp ror 1; --anticlockwise rotation

end if;

end if;

end process P2;

dout <= temp;

end Behavioral;
Program 5:

Write VHDL code to generate square waveform using DAC.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dacsqr is
Port ( clkin : in std_logic;
douta : out std_logic_vector(7 downto 0));
end dacsqr;

architecture Behavioral of dacsqr is

signal clk_div: std_logic_vector( 15 downto 0):=(others=>'0');
signal clk1: std_logic;
signal temp: std_logic_vector(7 downto 0);--:=(others=>'0');

begin
P1:process(clkin)
begin
if clkin'event and clkin = '1' then
clk_div <= clk_div + 1;
end if;
end process P1;

clk1 <= clk_div(15);

P2:process(clk1)
begin
 if clk1'event and clk1 = '1' then
temp <= not temp;
end if;
douta <= temp;
end process P2;
end Behavioral;
Program 6:

Write VHDL code to generate RAMP waveform using DAC.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dacramp is
Port ( clkin : in std_logic;
douta : out std_logic_vector(7 downto 0));
end dacramp;

architecture Behavioral of dacramp is

signal clk1: std_logic;
signal temp: std_logic_vector( 7 downto 0):=(others=>'0');
signal clk_div: std_logic_vector(15 downto 0):=(others=>'0');
begin

P1:process(clkin)
begin
if clkin'event and clkin = '1' then
clk_div <= clk_div + 1;
end if;
end process P1;

clk1 <= clk_div(8);

P3:process(clk1)
begin
if clk1'event and clk1 = '1' then
temp <= temp + 1;
douta <= temp;
end if;
end process P3;
end Behavioral;
Program 7:

Write HDL code to generate Triangle waveform using DAC.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dactri is
Port ( clkin : in std_logic;
douta : out std_logic_vector(7 downto 0));
end dactri;

architecture Behavioral of dactri is

signal clk1: std_logic;
signal temp: std_logic_vector( 7 downto 0):=(others =>'0');
signal clk_div:std_logic_vector(20 downto 0):=(others =>'0');
type temp_array is array(0 to 32) of std_logic_vector(7 downto 0);
signal tri_array: temp_array :=(X"00",X"10",X"20",X"30",X"40",X"50",

X"60",X"70",X"80",X"90",X"A0",X"B0",

X"C0",X"D0",X"E0",X"F0",X"FF",X"F0",

X"E0",X"D0",X"C0",X"B0",X"A0",X"90",

X"80",X"70",X"60",X"50",X"40",X"30",

X"20",X"10",X"00");
begin

P1:process(clkin)
begin
if clkin'event and clkin = '1' then
clk_div <= clk_div + 1;
end if;
end process P1;

clk1 <= clk_div(10);

P2:process(clk1)
variable data_loc:integer range 0 to 32 :=0;
begin
if clk1'event and clk1 = '1' then
if data_loc = 32 then
data_loc := 0;
else
data_loc := data_loc + 1;
end if;
end if;
temp <= tri_array(data_loc);
end process P2;

douta <= temp;

end Behavioral;
Program 8:

Write HDL code to generate Sin waveform using DAC.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dacsine is
Port ( clkin : in std_logic;
douta : out std_logic_vector(7 downto 0));
end dacsine;

architecture Behavioral of dacsine is

signal clk1: std_logic;
signal temp: std_logic_vector( 7 downto 0):=(others =>'0');
signal clk_div : std_logic_vector(15 downto 0):=(others =>'0');
type temp_array is array(0 to 255) of std_logic_vector(7 downto 0);

signal sine_array : temp_array :=

(X"7F",X"82",X"85",X"88",X"8B",X"8F",X"92",X"95",X"98",X"9B",X"9E",X"A1",X"A4",X"A7",X"AA
",X"AD",X"B0",X"B2",X"B5",X"B8",X"BB",X"BE",X"C0",X"C3",X"C6",X"C8",X"CB",X"CD",X"D0",X"
D2",X"D4",X"D7",X"D9",X"DB",X"DD",X"DF",X"E1",X"E3",X"E5",X"E7",X"E9",X"EA",X"EC",X"EE",
X"EF",X"F1",X"F2",X"F3",X"F5",X"F6",X"F7",X"F8",X"F9",X"FA",X"FB",X"FB",X"FC",X"FC",X"FD",X
"FD",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FE",X"FD",X"FD",X"FC",X"FC",X"
FB",X"FA",X"F9",X"F8",X"F7",X"F6",X"F5",X"F4",X"F3",X"F1",X"F0",X"EE",X"ED",X"EB",X"EA",X"E
8",X"E6",X"E4",X"E2",X"E0",X"DE",X"DC",X"DA",X"D8",X"D6",X"D3",X"D1",X"CE",X"CC",X"C9",X
"C7",X"C4",X"C2",X"BF",X"BC",X"BA",X"B7",X"B4",X"B1",X"AE",X"AB",X"A8",X"A5",X"A2",X"9F",
X"9C",X"99",X"96",X"93",X"90",X"8D",X"8A",X"87",X"84",X"81",X"7E",X"7A",X"77",X"74",X"71"
,X"6E",X"6B",X"68",X"65",X"62",X"5F",X"5C",X"59",X"56",X"53",X"50",X"4D",X"4A",X"47",X"45"
,X"42",X"3F",X"3C",X"3A",X"37",X"35",X"32",X"30",X"2D",X"2B",X"29",X"26",X"24",X"22",X"20"
,X"1E",X"1C",X"1A",X"18",X"16",X"14",X"13",X"11",X"10",X"0E",X"0D",X"0B",X"0A",X"09",X"08
",X"07",X"06",X"05",X"04",X"03",X"02",X"02",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00
",X"00",X"00",X"00",X"00",X"01",X"01",X"01",X"02",X"03",X"03",X"04",X"05",X"06",X"07",
X"08",X"09",X"0B",X"0C",X"0D",X"0F",X"10",X"12",X"13",X"15",X"17",X"19",X"1B",X"1D",X"1F",
X"21",X"23",X"25",X"27",X"2A",X"2C",X"2E",X"31",X"33",X"36",X"38",X"3B",X"3E",X"40",X"43",
X"46",X"49",X"4B",X"4E",X"51",X"54",X"57",X"5A",X"5D",X"60",X"63",X"66",X"69",X"6C",X"6F",
X"72",X"76",X"79" );

begin
P1:process(clkin)
begin
if clkin'event and clkin = '1' then
clk_div <= clk_div + 1;
end if;
end process P1;

clk1 <= clk_div(8);

P2:process(clk1)
variable data_loc:integer range 0 to 255 :=0;
begin
if clk1'event and clk1 = '1' then
if data_loc = 255 then
data_loc := 0;
else
data_loc := data_loc + 1;
end if;
end if;
 temp <= sine_array(data_loc);

end process P2;

douta <= temp;

end Behavioral;