Diseño Digital Problemas

BANCO DE REGISTROS
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BANCO_REGISTRO is
Port(selA,selB,selD: in std_logic_vector(1 downto 0);
clk, ena: in std_logic;
data: in std_logic_vector(7 downto 0);
A,B : out std_logic_vector(7 downto 0));
end BANCO_REGISTRO;
architecture solucion of BANCO_REGISTRO is

signal R0,R1,R2,R3: std_logic_vector(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if ena='1' then
case selD is
when "00" => R0<=DATA;
when others => R3<=DATA;
end case;
end if;
end if;
end process;
A<= R0 when selA="00" else

R1 when selA="01" else
R2 when selA="10" else R3;
with selB select B <= R0 when "00",

R1 when "01",
R2 when "10",
R3 when others;
end solucion;
SECUENCIA DE BITS 10011001 CON LOAD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cadenabits is
port(clk,load:in std_logic;
z: out std_logic);
end cadenabits;
architecture solucion of cadenabits is

signal cuenta:std_logic_vector(22 downto 0);
signal cuentita: integer range 7 to 0;
signal x:std_logic;
begin
with cuentita select z <= '1' when 0 | 3 | 4 | 7 ,

'0' when others;
process(clk)
begin
cuenta<=cuenta+1;
if cuenta=2500000 then
cuenta<=(others=>'0');
x<=not x;
end if;
end if;
end process;
process(x)
begin
if rising_edge(x) then
if load='1' then
cuentita<=cuentita+1;
if cuentita=8 then
cuentita<=0;
end if;
end if;
end if;
end process;
end solucion;
PERSONAS QUE ENTRAN Y SALEN DE UN LOCAL
library ieee;
entity cantidad_personas is
Port(clk,pe,ps: in std_logic;
unidades, decenas: buffer std_logic_vector(3 downto 0));
end cantidad_personas;
architecture solucion of cantidad_personas is

begin
process(clk)
begin
if pe='1' and ps='0' then
unidades<=unidades+1;
if unidades=9 then
unidades<="0000";
decenas<=decenas+1;
if decenas<=9 then
decenas<="0000";
end if;
end if;
elsif ps='1' and pe='0' then
unidades<=unidades-1;
if unidades<=0 then
unidades<="1001";
decenas<=decenas-1;
if decenas<=0 then
decenas<="1001";
end if;
end if;
end if;
end if;
end process;
end solucion;
CODIFICADOR DE PRIORIDAD
library ieee;
entity codificador_prioridad is
port(Q: in std_logic_vector(6 downto 0);
M: out std_logic_vector(2 downto 0));
end codificador_prioridad;
architecture solucion of codificador_prioridad is

begin
process(Q)
begin
if Q(6)='1' then M<="111";
elsif Q(5)='1' then M<="110";
elsif Q(4)='1' then M<="101";
elsif Q(3)='1' then M<="100";
elsif Q(2)='1' then M<="011";
elsif Q(1)='1' then M<="010";
elsif Q(0)='1' then M<="001";
else M<=(others=>'Z');
end if;
end process;
end solucion;
COMPARADOR DE 4 BITS (FORMA 1)

library ieee;
entity comparador4_bits2 is
port(A,B: in std_logic_vector(3 downto 0);
MAY,IGUAL,MEN: out std_logic);
end comparador4_bits2;
architecture solucion of comparador4_bits2 is

begin
IGUAL<='1' when A=B else '0';
MAY<='1' when A>B else '0';
MEN<='1' when A<B else '0';
end solucion;
COMPARADOR DE 4 BITS (FORMA 2)
library ieee;
entity comparador4_bits is
MAY,IGUAL,MEN: out std_logic);
end comparador4_bits;
architecture solucion of comparador4_bits is

begin
process(A,B)
begin
if(A=B) then IGUAL<='1'; else IGUAL<='0'; end if;
if(A>B) then MAY<='1'; else MAY<='0'; end if;
if(A<B) then MEN<='1'; else MEN<='0';end if;
end process;
end solucion;
PROBLEMA CONSEJO DE FACULTAD

library IEEE;
entity CONSEJO_FACULTAD is
Port(doc,alum,adm: in integer range 0 to 7;
z: out std_logic);
end CONSEJO_FACULTAD;
architecture solucion of CONSEJO_FACULTAD is

begin
process(doc,alum,adm)
begin
if doc>4 or alum>6 or adm>3 then z<='0';
elsif doc>=2 and alum>=4 and adm>=1 then z<='1';
else z<='0';
end if;
end process;
end solucion;
CONTADOR DE 0 A 2 CON SET QUE MANDA LA CUENTA A 10
library IEEE;
entity CONTA_0A20 is
Port(ena, set, clr,clk: in std_logic;
q:buffer std_logic_vector(4 downto 0));
end CONTA_0A20;
architecture solucion of CONTA_0A20 is

begin
process(clr,clk)
begin
if clr='1' then
q<="00000"; --no se activa nada
elsif falling_edge(clk) then
if set='1' then
q<="01010"; --se manda al numero 10
elsif ena='1' then
q<=q+2; --suma de 2 en 2
if q=20 then
q<="00000"; --se reinicia el conteo
end if;
end if;
end if;
end process;
end solucion;
CONTADOR UP DOWN DE 0 A 7 CON UN DISPLAY

library IEEE;
entity conta_0a7 is
Port(clk,ud: in std_logic;
display: out std_logic_vector(7 downto 0));
end conta_0a7;
architecture solucion of conta_0a7 is

signal x: std_logic;
signal y: std_logic_vector(2 downto 0);
signal cuenta: std_logic_vector(24 downto 0);
begin
process(clk)
begin
cuenta<=cuenta+1;
x<=not x;
end if;
end if;
end process;
process(x)
begin
if rising_edge(x) then
if ud='0' then
y<=y+1;
else
y<=y-1;
end if;
end if;
end process;
--pgfedcba
with y select display <= "11000000" when "000",
"11111001" when "001",
"10100100" when "010",
"10110000" when "011",
"10011001" when "100",
"10010010" when "101",
"10000011" when "110",
"11111000" when others;
end solucion;
CONTADOR CENTESIMAS DE SEGUNDOS Y SEGUNDOS CON LEDS
library ieee;
entity contador_segcent is
Port(clk,s_r,reset: in std_logic;
cent: buffer std_logic_vector(6 downto 0);
seg: buffer std_logic_vector(3 downto 0));
end contador_segcent;
architecture solucion of contador_segcent is

begin
process(clk)
begin
cuenta<=cuenta+1;
if cuenta=250 then
x<= not x;
end if;
end if;
end process;
process(x,reset)
begin
if reset='1' then
seg<=(others=>'0');
cent<=(others=>'0');
elsif rising_edge(x) then
if s_r='1' then
cent<=cent+1;
if cent=100 then
cent<=(others=>'0');
seg<=seg+1;
end if;
end if;
end if;
end process;
end solucion;
CONTADOR 0-99 CON 2 DISPLAYS
library ieee;
entity contador99_display is
port(clk,reset: in std_logic;
display,enable: out std_logic_vector(7 downto 0);
uni,dec: buffer std_logic_vector(3 downto 0));
end contador99_display;
architecture solucion of contador99_display is

signal display1, display2: std_logic_vector(7 downto 0);
begin
process(clk)
begin
cuenta<=cuenta+1;
x<=not x;
end if;
end if;
end process;
process(x,reset)
begin
if reset='1' then
uni<=(others=>'0');
dec<=(others=>'0');
elsif rising_edge(x) then
uni<=uni+1;
if uni=9 then
uni<=(others=>'0');
dec<=dec+1;
if dec=9 then
dec<=(others=>'0');
end if;
end if;
end if;
end process;
--pgfedcba
with uni select display1 <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",
"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11111000" when "0111",
"10000000" when "1000",
--pgfedcba
with dec select display2 <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",
"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11111000" when "0111",
"10000000" when "1000",
display <= display1 when x='0' else display2;
enable<= "11111110" when x='0' else "11111101";
end solucion;
DECODIFICADOR DE 3 A 8
library IEEE;
entity DEC3A8_ENA is
Port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
ENA : in std_logic;
Y : out std_logic_vector(7 downto 0));
end DEC3A8_ENA;
architecture Behavioral of DEC3A8_ENA is
signal ENTRADA: std_logic_vector(2 downto 0);
signal SALIDAS: std_logic_vector(7 downto 0);
begin
ENTRADA <= C & B & A;
with ENTRADA select SALIDAS <= "00000001" when "000",
"00000010" when "001",

"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
Y <= SALIDAS when ENA='1' else (others=>'0');
end Behavioral;
DECODIFICADOR DE 2 A 4
library IEEE;
entity DECO2A4 is
Port(SEL: in std_logic_vector(1 downto 0);
Y: out std_logic_vector(3 downto 0));
end DECO2A4;
architecture solucion of DECO2A4 is

begin
Y<= "0001" when SEL="00" else
"0010" when SEL="01" else
"0100" when SEL="10" else "1000";
end solucion;
DECODIFICADOR DE 7 SEGMENTOS
library ieee;
entity deco7 is
port(entrada: in std_logic_vector(3 downto 0);
end deco7;
architecture solucion of deco7 is

begin
with entrada select display <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",
"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11011000" when "0111",
"10000000" when "1000",
"10011000" when "1001",
"10001000" when "1010",
"10000011" when "1011",
"11000110" when "1100",
"10100001" when "1101",
"10000110" when "1110",
end solucion;
DECODIFICADOR CON PRIORIDAD

library IEEE;
entity decoder7_prioridad is
Port(switch:in std_logic_vector(3 downto 0);
sel: in std_logic_vector(2 downto 0);
display: out std_logic_vector(7 downto 0);
habilitador: out std_logic_vector(7 downto 0));
end decoder7_prioridad;
architecture solucion of decoder7_prioridad is

begin
with sel select habilitador <= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",

"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
with switch select display <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",

"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11011000" when "0111",
end solucion;
DESPLAZAMIENDO DERECHA-IZQUIERDA
library IEEE;
entity DESPLAZO1 is
Port(sel: in std_logic_vector(1 downto 0);
Q: out std_logic_vector(7 downto 0));
end DESPLAZO1;
architecture solucion of DESPLAZO1 is

begin
Q<= (others=>'0') when sel="00" else
data(3 downto 0) & data(7 downto 4) when sel="01" else
data(6 downto 0) & data(7) when sel="10" else data(0) & data(7
downto 1);
end solucion;
DISPLAY PALABRA FIEE

library IEEE;
entity display_fiee2015 is
Port(clk: in std_logic;
d0,d1,d2,d3: out std_logic_vector(7 downto 0));
end display_fiee2015;
architecture solucion of display_fiee2015 is

signal a,b,c,d: std_logic_vector(7 downto 0);
begin
process(clk)
begin
x<=not x;
if x='1' then
a<="10001110";
b<="11001111";
c<="10000110";
d<="10000110";
else
a<="10100100";
b<="11000000";
c<="11111001";
d<="10010010";
end if;
end if;
end process;
d3<=a;
d2<=b;
d1<=c;
d0<=d;
end solucion;
DISPLAY SPORTING CRISTAL EN 2 DISPLAYS

library IEEE;
entity display2_sc is
buzz: out std_logic;
display, enable: out std_logic_vector(8 downto 0));
end display2_sc;
architecture solucion of display2_sc is
begin
buzz<='1';
display<= "10010010" when x='0' else "11000110";
enable <= "11111110" when x='0' else "11111101";
process(clk)
begin
cuenta<=cuenta+1;
x<=not x;
end if;
end if;
end process;
end solucion;
DIVISOR DE CLOCK
library IEEE;
entity divisor is
Port(clk:in std_logic;
z: out std_logic);
end divisor;
architecture solucion of divisor is

signal cuenta1, cuenta2: std_logic_vector(1 downto 0);
begin
process(clk)
begin
cuenta1<=cuenta1+1;
cuenta2<=cuenta2+1;
if cuenta2=2 then
cuenta2<="00";
end if;
end if;
end process;
z<=clk when sel="00" else

cuenta1(0) when sel="01" else
cuenta2(1) when sel="10" else cuenta1(1);
end solucion;
DIVISOR DE 1 HZ
library ieee;
entity divisor1hz is
port(clk: in std_logic;
z: buffer std_logic);
end divisor1hz;
architecture solucion of divisor1hz is

begin
process(clk)
begin
cuenta<=cuenta+1;
z<=not z;
end if;
end if;
end process;
end solucion;
DIVISOR 1KHZ
library IEEE;
entity DIVISOR1K is
Port(clk,push: in std_logic;
z:buffer std_logic);
end DIVISOR1K;
architecture solucion of DIVISOR1K is
begin
process(clk,push)
begin
cuenta<=cuenta+1;
z<=not z;
end if;
if push='1' then
cuenta<=cuenta+1;
z<=not z;
end if;
end if;
end if;
end process;
end solucion;
DUTY CICLE
library ieee;
entity duty_cycle is
z: out std_logic);
end duty_cycle;
architecture solucion of duty_cycle is

begin
process(clk)
begin
cuenta<=cuenta+1;
z<='1';
end if;
case sel is
when "00" => if cuenta=1000 then z<='1'; else z<='0'; end if;
when others => if cuenta=9000 then z<='1'; else z<='0'; end if;
end case;
end if;
end process;
end solucion;
FLIP-FLOP TIPO D
library IEEE;
entity FF_D is
Port(clk,clr,D: in std_logic;
Q: out std_logic);
end FF_D;
architecture solucion of FF_D is

begin
process(clk,clr)
begin
if clr='1' then
Q<='0';
elsif rising_edge(clk) then
Q<=D;
end if;
end process;
end solucion;
GENERADOR DE PULSOS
library ieee;
entity generador is
z: out std_logic);
end generador;
architecture solucion of generador is

signal cuenta: integer range 19 to 0;
begin
with cuenta select z <= '1' when 0 | 5 | 6 | 10 | 11 | 12 | 15 | 16 | 17 | 18 ,
'0' when others;
process(clk)
begin
cuenta <= cuenta + 1;
if cuenta=19 then
cuenta<=0;
end if;
end if;
end process;
end solucion;
PALABRA “HOLA PERU” EN 4 DISPLAY

library IEEE;
entity hola_peru is
habilitador: out std_logic_vector(7 downto 0);
end hola_peru;
architecture solucion of hola_peru is

signal x: std_logic_vector(1 downto 0);
signal y: std_logic_vector(2 downto 0);
begin
process(clk)
begin
cuenta<=cuenta+1;
cuenta<=0;
x<=x+1;
y<=y+1;
end if;
end if;
end process;
with x select habilitador <= "11110111" when "00",

"11111011" when "01",
"11111101" when "10",
with y select display <= "10001001" when "000",

"11000000" when "001",
"11000111" when "010",
"11001000" when "011",
"10001100" when "100",
"10000110" when "101",
"10001000" when "110",
end solucion;
EJEMPLO DE MAQUINAS DE ESTADO HECHO EN CLASE

library IEEE;
entity maquina1 is
Port(D,clk: in std_logic;
Q: out std_logic);
end maquina1;
architecture solucion of maquina1 is

TYPE estados is (S0,S1,S2,S3,S4,S5);
SIGNAL EP,ES: estados;
begin
process(clk)
begin
EP<=ES;
end if;
end process;
process(EP,D)
begin
ES<=EP;
case EP is
when S0=> Q<='0';
if D='1' then ES<=S1; else ES<=S0; end if;
when S1=> Q<='0';
when S2=> Q<='0';
when S3=> Q<='0';
when S4=> Q<='0';
when S5=> Q<='0';
end case;
end process;
end solucion;
EJEMPLO 2 DE MAQUINAS DE ESTADO PARA UNA SECUENCIA DE BITS

library IEEE;
entity MAQUINA2 is
Port(clk,d: in std_logic;
z:out std_logic);
end MAQUINA2;
architecture solucion of MAQUINA2 is

signal q: std_logic_vector(5 downto 0);
begin
process(clk)
begin
q<= d & q(5 downto 1);
end if;
end process;
z<='1' when q="101101" else '0';
end solucion;
EJEMPLO 3 DE MAQUINAS DE ESTADO

library ieee;
entity maquina3 is
port(clk,boton: in std_logic;
z: out std_logic);
end maquina3;
architecture solucion of maquina3 is

signal q: std_logic;
begin
process(boton)
begin
if falling_edge(boton) then
q<= not q; --alterna 1 y 0
end if;
end process;
z<= clk when q='1' else '0'; --toma valor de clk o 0
end solucion;
CUADRO EN UNA MATRIZ DE 8X8

library IEEE;
entity matriz8 is
fila, columna: out std_logic_vector(7 downto 0));
end matriz8;
architecture solucion of matriz8 is

signal x: std_logic_vector(2 downto 0);
begin
process(clk)
begin
cuenta<=cuenta+1;
x<= x+1;
end if;
end if;
end process;
with x select fila <= "00000000" when "000"|"111",

with x select columna <= "11111110" when "000",

"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
end solucion;
MUX 2 A 1
library IEEE;
entity MUX2A1 is
Port(A,B,SEL: in std_logic;
Z1,Z2: out std_logic);
end MUX2A1;
architecture solucion of MUX2A1 is

begin
Z1<=(A and not sel)or(b and sel);
Z2<= A WHEN sel='0' else B;
end solucion;
MUX DE 4 A 1
library IEEE;
entity mux4a1_fd is
Port(e: in std_logic_vector(3 downto 0);
z: out std_logic);
end mux4a1_fd;
architecture solucion of mux4a1_fd is
begin
z<= e(0) when sel="00" else
e(1) when sel="01" else
e(2) when sel="10" else e(3);
end solucion;
MUX DE 8 A 1
library IEEE;
entity mux8a1_e is
port(entradas: in std_logic_vector(7 downto 0);
selector: in std_logic_vector(2 downto 0);
z: out std_logic);
end mux8a1_e;
architecture solucion of mux8a1_e is

component mux4a1_fd
Port(e: in std_logic_vector(3 downto 0);
z: out std_logic);
end component;
signal x,y: std_logic;
signal NODO: std_logic_vector(3 downto 0);
signal NODITO: std_logic_vector(1 downto 0);
begin
NODO <= "00" & y & x;
NODITO <= '0' & selector(2);
U0: mux4a1_fd port map (entradas(3 downto 0), selector(1 downto 0),x);
U2: mux4a1_fd port map (entradas(7 downto 4), selector(1 downto 0),y);
U1: mux4a1_fd port map (NODO, NODITO,z);
end solucion;
PWM
library ieee;
entity PWM is
port(clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
z: out std_logic);
end PWM;
architecture solucion of PWM is

begin
process(clk)
begin
cuenta<=cuenta+1;
if cuenta=1000 then
end if;
case sel is
when others => if cuenta=1000 then z<='1'; else z<='0'; end if;
end case;
end if;
end process;
end solucion;
REGISTRO DE 8 BITS CON ENABLE

library IEEE;
entity register8_ena is
Port(ena,clk: in std_logic;
q: buffer std_logic_vector(7 downto 0));
end register8_ena;
architecture solucion of register8_ena is

begin
process(clk)
begin
if ena='1' then
if sel="00" then
q<=data;
elsif sel="01" then
q<=q(6 downto 0) & q(7);
elsif sel="10" then
q<=q(0) & q(7 downto 1);
else
q<=q+1;
end if;
end if;
end if;
end process;
end solucion;
REGISTRO DE 8 BITS CON CLEAR Y ENABLE

library IEEE;
entity registro_8 is
Port(clk,ena,clr: in std_logic;
q: out std_logic_vector(7 downto 0));
end registro_8;
architecture solucion of registro_8 is

begin
process(clr,clk)
begin
if clr='1' then
q<=(others=>'0');
if ena='1';
q<=data;
end if;
end if;
end process;
end solucion;
SEMAFORO HECHO EN CLASE CON MAQUINA DE ESTADO

library IEEE;
entity semaforo is
Port(clk,stop :in std_logic;
R,A,V: out std_logic);
end semaforo;
architecture solucion of semaforo is

SIGNAL contador:std_logic_vector(4 downto 0);
TYPE estados is (S0,S1,S2);
SIGNAL EP,ES: estados;
SIGNAL ROJO: std_logic;
begin
process(clk)
begin
EP<=ES;
case EP is
when S0=> contador<="00000";
when OTHERS=> contador<=contador+1;
end case;
end if;
end process;
process(EP,STOP)
begin
ES<=EP;
case EP is
when S0=> ROJO<='0'; A<='0'; V<='1';
if stop='1' then
ES<=S1;
else ES<=S0;
end if;
when S1=> ROJO<='0'; A<='1'; V<='0';
if contador=2 then
ES<=S2;
else ES<=S1;
end if;
when S2=> ROJO<='1'; A<='0'; V<='0';
if contador=22 then
ES<=S0;
else ES<=S2;
end if;
end case;
end process;
R<=ROJO when contador < 17 else clk;
end solucion;
DOS SEMAFOROS CON MAQUINA DE ESTADOS

library IEEE;
entity semaforo2 is
port(clk: in std_logic;
R,V,Ro,Am,Ve: out std_logic);
end semaforo2;
architecture solucion of semaforo2 is

signal contador: std_logic_vector(5 downto 0);
type estados is (S0,S1,S2);
signal EP,ES: estados;
signal ROJO: std_logic;
begin
process(clk)
begin
EP<=ES;
case EP is
when others=> contador<=contador+1;
end case;
end if;
end process;
process(EP)
begin
ES<=EP;
case EP is
when S0=> ROJO<='1'; V<='0'; Ro<='0'; Am<='0'; Ve<='1';
if contador=30 then ES<=S1; else ES<=S0; end if;
end case;
end process;
R<=ROJO when contador<47 else clk;
end solucion;
DOS SEMAFOROS CON SENTENCIA IF

library IEEE;
entity semaforo_conif is
R,V:out std_logic;
ro,am,ve: buffer std_logic);
end semaforo_conif;
architecture solucion of semaforo_conif is

signal rojo: std_logic;
begin
process(clk)
begin
cuenta<=cuenta+1;
if cuenta=0 then
rojo<='0';am<='0';ve<='1';
elsif cuenta=29 then
rojo<='0'; am<='1';ve<='0';
rojo<='1'; am<='0'; ve<='0';
cuenta<=0;
end if;
end if;
end process;
ro<=rojo when cuenta<47 else clk;

R<='1' when ve='1' else '0';
V<='1' when rojo='1' or am='1' else '0';
end solucion;
VISOR
library ieee;
entity visor is
E0,E1,E2,E3,E4,E5,E6,E7: in std_logic_vector(3 downto 0);
display: out std_logic_vector(7 downto 0);
habilitador: out std_logic_vector(7 downto 0));
end visor;
architecture solucion of visor is

component deco7
port(entrada: in std_logic_vector(3 downto 0);
end component;
signal x:std_logic_vector(2 downto 0);
signal y:std_logic_vector(3 downto 0);
begin
process(clk)
begin
cuenta<=cuenta+1;
x<= x + 1;
end if;
end if;
end process;
with x select y <= E0 when "000",

E1 when "001",
E2 when "010",
E3 when "011",
E4 when "100",
E5 when "101",
E6 when "110",
E7 when others;
U2: deco7 port map(y, display);

with x select habilitador <= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
end solucion;
CONTADOR EN CODIGO GRAY DE 4 BITS

library ieee;
entity CONTADORGRAY_4BITS is
port(clk,clr,ena: in std_logic;
grey: out std_logic_vector(3 downto 0));
end CONTADORGRAY_4BITS;
architecture solucion of CONTADORGRAY_4BITS is

signal cuenta,x : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clr='1' then
if ena='1' then
cuenta<=cuenta+1;
x<=cuenta xor ('0' & cuenta(3 downto 1));
if cuenta=14 then
end if;
end if;
end if;
end process;
grey<=x;
end solucion;
DIVISOR DE FRECUENCIA 2017-II
library ieee;
entity DIVISOR_FRECUENCIA2017II is
port(clk:in std_logic;
z:out std_logic);
end DIVISOR_FRECUENCIA2017II;
architecture solucion of DIVISOR_FRECUENCIA2017II is

signal a: std_logic;
signal b,c: std_logic_vector(1 downto 0);
signal d,e: std_logic_vector(2 downto 0);
begin
process(clk)
begin
a<=not a;
b<=b+1; if b=2 then b<="00"; end if;
c<=c+1; if c=3 then c<="00"; end if;
d<=d+1; if d=4 then d<="000"; end if;
e<=e+1; if e=5 then e<="000"; end if;
end if;
end process;
z<= '0' when sel="000" else

clk when sel="001" else
a when sel="010" else
b(1) when sel="011" else
c(1) when sel="100" else
d(2) when sel="101" else
e(2) when sel="110" else '1';
end solucion;
CONTADOR FLANCO SUBIDA BAJADA, PLANCHA DE GUTY

library ieee;
entity flanco_subidabajada is
port( clk: in std_logic;
z2,z1,z0: buffer std_logic);
end flanco_subidabajada;
architecture solucion of flanco_subidabajada is

signal cuenta1,cuenta2: std_logic_vector(3 downto 0);
begin
z2<='1' when cuenta1=0 or cuenta2=2 else '0';
z1<='1' when cuenta1=3 or cuenta2=0 else '0';
z0<='1' when z1='1' and z2='0' else '0';
process(clk)
begin
cuenta1<=cuenta1+1;
if cuenta1=4 then
cuenta1<="0000";
end if;
end if;
if falling_edge(clk) then
cuenta2<=cuenta2+1;
if cuenta2=4 then
cuenta2<="0000";
end if;
end if;
end process;
end solución;
SUMA CON ACARREO

library ieee;
entity suma_acarreo is
ci: in std_logic;
s: out std_logic_vector(3 downto 0);
co: out std_logic);
end suma_acarreo;
architecture solucion of suma_acarreo is

signal suma: std_logic_vector(4 downto 0);
begin
suma<=('0'&A)+B+ci;
S<=suma(3 downto 0);
co<=suma(4);
end solucion;
SUMA DE 8 BITS CON SIGNO

library ieee;
entity suma8bits_signo is
port(A,B: in unsigned (7 downto 0);
C: in signed(7 downto 0);
D: in std_logic_vector(7 downto 0);
S: out unsigned (8 downto 0);
T: out signed (8 downto 0);
U: out signed (7 downto 0);
V: out std_logic_vector(8 downto 0));
end suma8bits_signo;
architecture solucion of suma8bits_signo is

begin
S<=('0' & A) + ('0' & B);
T<=A+C;
U<=C+SIGNED(D);
V<=C-SIGNED(D);
end solucion;
FULL ADDER DE 2 BITS

library ieee;
entity fulladder_2bits is
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end fulladder_2bits;
architecture solucion of fulladder_2bits is

begin
sum<=(a xor b) xor c;
carry <= (a and b) or (c and (a xor b));
end solucion;
FULL ADDER DE 4 BITS

library ieee;
entity fulladder_4bits is
port(a,b: in std_logic_vector(3 downto 0);
cin: in std_logic;
sum: out std_logic_vector(3 downto 0);
cout,v: out std_logic);
end fulladder_4bits;
architecture solucion of fulladder_4bits is

signal c: std_logic_vector(4 downto 1);
component fulladder_2bits
port(a,b,c: in std_logic;
sum,carry: out std_logic);
end component;
begin
FA0: fulladder_2bits port map (a(0),b(0),cin,sum(0),c(1));
FA1: fulladder_2bits port map (a(1),b(1),c(1),sum(1),c(2));
v<=c(3) xor c(4);
cout<=c(4);
end solucion;
REGISTRO DESPLAZADOR CON FF TIPO D

library ieee;
entity registro_d is
port(clk,d,rst: in std_logic;
q: out std_logic);
end registro_d;
architecture solucion of registro_d is

signal x:std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if rst='1' then
q<='0';
x<=x(2 downto 0) & d;
q<=x(3);
end if;
end process;
end solucion;

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BANCO DE REGISTROS

architecture solucion of BANCO_REGISTRO is

A<= R0 when selA="00" else

with selB select B <= R0 when "00",

architecture solucion of cadenabits is

with cuentita select z <= '1' when 0 | 3 | 4 | 7 ,

architecture solucion of cantidad_personas is

architecture solucion of codificador_prioridad is

COMPARADOR DE 4 BITS (FORMA 1)

architecture solucion of comparador4_bits2 is

architecture solucion of comparador4_bits is

PROBLEMA CONSEJO DE FACULTAD

architecture solucion of CONSEJO_FACULTAD is

architecture solucion of CONTA_0A20 is

CONTADOR UP DOWN DE 0 A 7 CON UN DISPLAY

architecture solucion of conta_0a7 is

architecture solucion of contador_segcent is

architecture solucion of contador99_display is

display <= display1 when x='0' else display2;

enable<= "11111110" when x='0' else "11111101";

"00000010" when "001",

architecture solucion of DECO2A4 is

architecture solucion of deco7 is

DECODIFICADOR CON PRIORIDAD

architecture solucion of decoder7_prioridad is

"11110111" when "011",

"10100100" when "0010",

architecture solucion of DESPLAZO1 is

DISPLAY PALABRA FIEE

architecture solucion of display_fiee2015 is

DISPLAY SPORTING CRISTAL EN 2 DISPLAYS

architecture solucion of divisor is

z<=clk when sel="00" else

architecture solucion of divisor1hz is

architecture solucion of duty_cycle is

architecture solucion of FF_D is

architecture solucion of generador is

PALABRA “HOLA PERU” EN 4 DISPLAY

architecture solucion of hola_peru is

with x select habilitador <= "11110111" when "00",

with y select display <= "10001001" when "000",

EJEMPLO DE MAQUINAS DE ESTADO HECHO EN CLASE

architecture solucion of maquina1 is

EJEMPLO 2 DE MAQUINAS DE ESTADO PARA UNA SECUENCIA DE BITS

architecture solucion of MAQUINA2 is

EJEMPLO 3 DE MAQUINAS DE ESTADO

architecture solucion of maquina3 is

CUADRO EN UNA MATRIZ DE 8X8

architecture solucion of matriz8 is

with x select fila <= "00000000" when "000"|"111",

with x select columna <= "11111110" when "000",

architecture solucion of MUX2A1 is

architecture solucion of mux8a1_e is

architecture solucion of PWM is

REGISTRO DE 8 BITS CON ENABLE

architecture solucion of register8_ena is

REGISTRO DE 8 BITS CON CLEAR Y ENABLE

architecture solucion of registro_8 is

SEMAFORO HECHO EN CLASE CON MAQUINA DE ESTADO

architecture solucion of semaforo is

DOS SEMAFOROS CON MAQUINA DE ESTADOS

architecture solucion of semaforo2 is

DOS SEMAFOROS CON SENTENCIA IF