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DISEÑO DIGITAL
Ing. Alfredo Granados Ly
I. Procedimiento
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity examen1 is
process(x)
begin
if rising_edge(x) then
contador2 <= contador2 + 1;
if contador2 = 50 then
contador2 <= (others => '0');
ena <= not ena;
end if;
end if;
end process;
process(x)
begin
if rising_edge(x) then
contmult <= contmult + 1;
if contmult = 4 then
contmult <= (others => '0');
end if;
end if;
end process;
--Multiplexado de la letra S
process(contmult)
begin
if ena = '1' then
case contmult is
when "000" => leds <= "011001001111";
when "001" => leds <= "100100110111";
when "010" => leds <= "100100111011";
when "011" => leds <= "100100111101";
when others => leds <= "010011011110";
end case;
end if;
end process;
end solucion;
Universidad Nacional Mayor de San de San Marcos
FACULTAD DE INGENIERIA ELECTRÓNICA Y ELÉCTRICA
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flipflop is
port( clk: in std_logic;
rst: in std_logic;
Q: buffer std_logic_vector(15 downto 0));
end flipflop;
begin
process(clk,rst)
begin
if rst = '0' then
Q <= "0000000000000001";
elsif rising_edge(clk) then
Q(1) <= Q(0);
Q(2) <= Q(1);
Q(3) <= Q(2);
Q(4) <= Q(3);
Q(5) <= Q(4);
Q(6) <= Q(5);
Q(7) <= Q(6);
Q(8) <= Q(7);
Q(9) <= Q(8);
Q(10) <= Q(9);
Q(11) <= Q(10);
Q(12) <= Q(11);
Q(13) <= Q(12);
Q(14) <= Q(13);
Q(15) <= Q(14);
Q(0) <= Q(15);
end if;
end process;
end solucion;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ruleta is
port( clk, rst, dir, ena: in std_logic;
q: buffer std_logic_vector(15 downto 0));
end ruleta;
Universidad Nacional Mayor de San de San Marcos
FACULTAD DE INGENIERIA ELECTRÓNICA Y ELÉCTRICA