Computer Architecture &

Digital Hardware Design

(ECD09)
(Practical file)

Prem kumar
ECE III
2016UEC2135
 Index
1. Characterization of Logic Family. Find out logic threshold values and
noise margins. Delay time measurement of inverter using ring
oscillator.
2. Design, model and test using VHDL, a Sign magnitude adder, BCD
incrementor, Gray Counter and LFSR based random number generator.
3. Design model and test using VHDL a single switch and keypad matrix
de-bouncing system.
4. Design and model using VHDL, the following LED multiplexing
schemes: regular LED multiplexing, Charlieplexed LED multiplexing
Experiment 1(A)
Aim: Characterization of Logic Family. Find out logic threshold values
and noise margins.
Apparatus Required:74HC04(NOT
gate),DSO,probes,wires,breadboard,multimeter,power
supply,potentiometer
Theory:
Threshold voltages- Logic gate circuits are designed to input and output
only two types of signals: “high” (1) and “low” (0), as represented by a
variable voltage: full power supply voltage for a “high” state and zero voltage
for a “low” state. In a perfect world, all logic circuit signals would exist at
these extreme voltage limits, and never deviate from them (i.e., less than full
voltage for a “high,” or more than zero voltage for a “low”). However, in
reality, logic signal voltage levels rarely attain these perfect limits due to stray
voltage drops in the transistor circuitry, and so we must understand the signal
level limitations of gate circuits as they try to interpret signal voltages lying
somewhere between full supply voltage and zero.
From the graph:
RESULT:
VIH (High level input voltage) =2.2V
VIL (Low level input voltage) =0.7 V
VOH (High level output voltage) =4.4V
VOL (Low level output voltage) =0.17 V
 EXPERIMENT-1(B)

AIM: Delay time measurement of inverter using ring oscillator.

Apparatus Required: 2*74HC04(NOT
gate),DSO,probes,wires,breadboard,power supply,potentiometer

Theory:
A ring oscillator is a device composed of an odd number of NOT
gates in a ring, whose output oscillates between two voltage levels,
representing true and false. The NOT gates, or inverters, are attached
in a chain and the output of the last inverter is fed back into the first.
Observations:
The oscillation frequency of an oscillator can be calculated as :
td=1/2*n*f
which n is number of stages and td is delay time of stages.

For n=3: f=90Mhz => td=1.85ns

For n=5: f=71Mhz => td=1.41ns
For n=7: f=34Mhz => td=2.04ns
For n=9: f=23.5Mhz => td=2.36ns
For n=11: f=16Mhz => td=2.84ns

RESULT:
Td(avg)=2.1ns
 EXPERIMENT-2
AIM: Design, model and test using VHDL, a Sign magnitude adder,
BCD incrementor, Gray Counter and LFSR based random number
generator.

CODE:(A)LFSR:

entity lfsr is
Port ( a : out STD_LOGIC_vector(3 downto 0):="0001";
clk : in STD_LOGIC);
end lfsr;

architecture Behavioral of lfsr is

signal test : std_logic_vector(10 downto 0):="00000000001";
begin
process(clk)
begin
if rising_edge(clk) then
test(10 downto 1)<=test(9 downto 0);
test(0)<=test(10) xor test(0);
end if;
end process;
a<=test(7 downto 4);
end Behavioral;

SIMULATION:

CODE:(B)GRAY COUNTER

entity graycounter is
port( clk :in std_logic;
op :buffer std_logic_vector(3 downto 0));
end graycounter;

architecture Behavioral of graycounter is

begin
process(clk)
variable test : std_logic_vector(3 downto 0):= "0000";
variable output: std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
output(3) :=test(3);
output(2) := test(3) xor test(2);
output(1) := test(2) xor test(1);
output(0) := test(1) xor test(0);
test := test +1;
end if;
op<=output;
end process;

end Behavioral;

SIMULATION:
 EXPERIMENT-3
AIM: Design model and test using VHDL a single switch de-bouncing
system.
CODE:

entity debounce is
Port (
ip: in std_logic;
clk : in std_logic;
op : out std_logic);
end debounce;

architecture Behavioral of debounce is

Signal a, b, c: std_logic;
begin
Process(clk)
begin
If rising_edge(clk) then
a <= ip;
b <= a;
c <= b;
end if;
end process;
op <= a and b and c;
end Behavioral;
SIMULATION:
 EXPERIMENT-4
AIM: Design and model using VHDL, the following LED multiplexing
schemes: regular LED multiplexing, Charlieplexed LED multiplexing

CODE:

entity led is
port ( p : in std_logic_vector(5 downto 0) := "111111" ;
V : in std_logic;
reset : in std_logic := '1' ;
r : out std_logic_vector(2 downto 0));

end led;

architecture Behavioral of led is

signal m : std_logic_vector(5 downto 0);

signal t1,t2,t3 : std_logic;
signal c : std_logic_vector(5 downto 0);
signal s : std_logic_vector(2 downto 0);
signal state : integer range 0 to 5 :=0;

component mux1
Port ( in1 : in std_logic; -- mux input1
in2 : in std_logic; -- mux input2
in3 : in std_logic; -- mux input3
in4 : in std_logic; -- mux input4
sel : in std_logic_vector(1 downto 0); -- selection line
dataout : out std_logic); -- output data
end component;

component tbuf1
port( A,EN : in std_logic;
Y : out std_logic);
end component;

begin

muxa : mux1 port map (m(0),m(4),'0','0',c(1 downto 0),t1);

muxb : mux1 port map (m(1),m(2),'0','0',c(3 downto 2),t2);
muxc : mux1 port map (m(3),m(5),'0','0',c(5 downto 4),t3);

tbufa : tbuf1 port map (t1,s(0),r(0));

tbufb : tbuf1 port map (t2,s(1),r(1));
tbufc : tbuf1 port map (t3,s(2),r(2));

p1 : process(p,V,reset)
begin
if ( rising_edge(V) and reset ='1') then
m <= p ;
if (state < 5) then
state <= state + 1;
else
state <= 0 ;
end if;
end if;
end process;

p2 : process(state,m)
begin
case state is
when 0 =>
if state = 0 then
s<="110" ;
c<="001100" ;
end if;

when 1=>
if state = 1 then
s<="110" ;
c<="110000" ;
end if;

when 2=>
if state = 2 then
s<="011" ;
c<="000111" ;
 end if;

when 3=>
if state = 3 then
s<="011" ;
c<="001100" ;
end if;

when 4=>
if state = 4 then
s<="101" ;
c<="010011" ;
end if;

when 5=>
if state = 5 then
s<="101" ;
c<="110001" ;
end if;
when others =>
s<= "000";
c<= "000000";
end case;
end process;

end Behavioral;
SIMULATION: