Instituto Tecnológico de Santo Domingo (INTEC)

Clave: IEC208L

Sección: 3

Tema:

BCD con Contador en VHDL

Nombre

Gian Susana Sánchez

ID:1099881

Asignatura: FUNDAMENTOS ELECTRÓNICA DIGITAL

Nombre del profesor/a: YOBANY DIAZ ROQUE

Objetivo: BCD con Contador en VHDL

Procedimiento

Diseño

-- Code your design here

library IEEE;

use IEEE.std_logic_1164.all;

entity clk_1Hz is

port (clk_100MHz : in std_logic;

SSD : out std_logic_vector(6 downto 0));

end entity;

architecture logic_flow of clk_1Hz is

signal count : natural range 1 to 50_000_000;

signal digit : natural range 0 to 9;

signal clk_1Hz: std_logic;

begin

process(clk_100MHz)

begin

if (rising_edge(clk_100MHz)) then

count <= count + 1;

if(count = 50_000_000) then

clk_1Hz <= not clk_1Hz;

count <= 1;

end if;

end if;
 end process;

process(clk_1Hz)

begin

if (digit > 9) then

digit <= 0;

else

digit <= digit + 1;

end if;

end process;

SSD <= "0000001" when digit = 0 else

"1001111" when digit = 1 else

"0010010" when digit = 2 else

"0000110" when digit = 3 else

"1001100" when digit = 4 else

"0100100" when digit = 5 else

"0100000" when digit = 6 else

"0001111" when digit = 7 else

"0000000" when digit = 8 else

"0000100" when digit = 9;

end logic_flow;

TestBench:

-- Code your testbench here

library IEEE;

use IEEE.std_logic_1164.all;
entity testbench is

-- empty

end testbench;

architecture tb of testbench is

-- DUT component

component clk_1Hz is

port(clk_100MHz : in std_logic;

SSD : out std_logic_vector(6 downto 0));

end component;

signal clk_100MHz_in : std_logic;

signal SSD_out : std_logic_vector(6 downto 0);

begin

-- Connect DUT

DUT: clk_1Hz port map(clk_100MHz_in, SSD_out);

CLK_gen: process

begin

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

 clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

clk_100MHz_in <= '1';

wait for 5 ns;

clk_100MHz_in <= '0';

wait for 5 ns;

assert false report "Test done." severity note;

wait;

end process CLK_gen;

end tb;