EE529

EMBEDDED SYSTEMS
Assignment-3

Submitted by submitted to
Aditi Gupta Dr. Shubhajit Roy Chowdhary
DD23015 SCEE
M.Tech(R) + PhD
Q1. Consider a Mealy type finite state machine that accepts all binary words of the format 1102
where 1 and 2 are binary strings of arbitrary length and may possibly be null strings also. The state
machine produces a binary „1‟ output when the system switches to the final state, otherwise it
produces a „0‟ output. There is also a master reset input that when set to logic high switches the
system to the initial state. Draw the state transition graph of the finite state machine annotating the
edges with appropriate input / output pairs. Write a suitable VHDL program to model the state
machine.

Q2. Read the following paragraph and answer the questions that follow: A sequence detector is a
synchronous sequential logic circuit that checks for a specific pattern in an input string. Consider a
sequence detector implemented as a Mealy type finite state machine. The circuit has one input X and
one output Z. The circuit produces an output 0 unless the input is 0 following a sequence of exactly
two 0 inputs followed by a 1 input.
Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC;
z : out STD_LOGIC);
end seq_detector;

architecture Behavioral of seq_detector is

type statetype is (s0, s1, s2,s3);
signal state , next_state: statetype := s0;
begin
process(reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process(state, x)
begin
case state is
when s0 =>
if x = '0' then
next_state <= s1;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s1 =>
if x = '0' then
next_state <= s2;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s2 =>
if x = '1' then
next_state <= s3;
z<= '0';
else
next_state <= s2;
z <= '0';
end if ;
when s3 =>
if x = '1' then
next_state <= s0;
z<= '0';
else
next_state <= s1;
z <= '1';
end if ;
end case;
end process ;
end Behavioral;

(A) Specify the output sequence for the input sequence X=0010
Ans:- as mentioned in the question this fsm is to detect 0 following exactly two consecutive 0 and then 1
that is the sequence X= 0010. So output will be Z =00001
(B) Let X=M00010, where M represents an input sequence not ending in 00. Find the last five bit
sequence in the output string Z.
Ans:- Let M= 01011 so x = 0101100010, z= 0000000001 last five bits are 00001

(C) Specify the output string Z for an input string X=0010010000100

Ans:- for the given x , Z = 0001001000010

Q3 . Model a finite state machine using VHDL that can recognize the pattern “10101101”.
code:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
w : in STD_LOGIC;
z : out STD_LOGIC);
end seq_detector;

architecture Behavioral of seq_detector is

type statetype is (s0, s1, s2, s3, s4, s5, s6, s7);
signal state , next_state: statetype := s0;
begin
process(reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process(state, w)
begin
case state is
when s0 =>
if w = '1' then
next_state <= s1;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s1 =>
if w = '0' then
next_state <= s2;
z<= '0';
else
next_state <= s1;
z <= '0';
end if ;
when s2 =>
if w = '1' then
next_state <= s3;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s3 =>
if w = '0' then
next_state <= s4;
z<= '0';
else
next_state <= s1;
z <= '0';
end if ;
when s4 =>
if w = '1' then
next_state <= s5;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s5 =>
if w = '1' then
next_state <= s6;
z<= '0';
else
next_state <= s4;
z <= '0';
end if ;
when s6 =>
if w = '0' then
next_state <= s7;
z<= '0';
else
next_state <= s1;
z <= '0';
end if ;
when s7 =>
if w = '1' then
next_state <= s1;
z<= '1';
else
next_state <= s0;
z <= '0';
end if ;

end case;
end process ;
end Behavioral;

Simulation:-
Q4. Design an FSM which takes a synchronized serial input IN (presented LSB first) and outputs a
serial bit stream OUT which represents the input plus 3. For example, if the input were 10102 the
output stream would be 11012. (Note that there is an output bit for every input bit. In the idle state on
RESET, a zero is output.)
Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity seq_plus3 is
port(
enable: in std_logic;
X, CLK: in std_logic;
Z: out std_logic);
end seq_plus3;
architecture Behavioral of seq_plus3 is
type state_type is (S0, S1, S2, S3, S4, S5, S6);
signal State, Nextstate: state_type;

begin
process(State, X)
begin
case State is
when S0 =>
if X = '0' then Z <= '1'; Nextstate <= S1;
else Z <= '0'; Nextstate <= S2; end if;
when S1 =>
if X = '0' then Z <= '1'; Nextstate <= S3;
else Z <= '0'; Nextstate <= S4; end if;
when S2 =>
if X = '0' then Z <= '0'; Nextstate <= S4;
else Z <= '1'; Nextstate <= S4; end if;
when S3 =>
if X = '0' then Z <= '0'; Nextstate <= S5;
else Z <= '1'; Nextstate <= S5; end if;
when S4 =>
if X = '0' then Z <= '1'; Nextstate <= S5;
else Z <= '0'; Nextstate <= S6; end if;
when S5 =>
if X = '0' then Z <= '0'; Nextstate <= S0;
else Z <= '1'; Nextstate <= S0; end if;
when S6 =>
if X = '0' then Z <= '1'; Nextstate <= S0;
else Z <= '0'; Nextstate <= S0; end if;
when others => null;
end case;
end process;

process (enable, CLK)

begin
if enable = '0' then
State <= S0;
elsif rising_edge (CLK) then
State <= Nextstate;
end if;
end process;
end Behavioral;

Simulation:-
Note :- LSB—> MSB(X =1010 is shown as 0101 and Z= 1101 is shown as 1011 from left to right )
Q5. Design a Moore FSM which outputs a single high pulse of width one clock cycle every time the
synchronized input signal START changes from 0 to 1.
Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity detector_0to1 is
Port (reset : in STD_LOGIC;
clk : in STD_LOGIC;
START : in STD_LOGIC;
z : out STD_LOGIC);
end detector_0to1;

architecture Behavioral of detector_0to1 is

type StateType is (s0, s1, s2);
signal state, next_state : StateType := s0;
signal pulseCounter : natural := 0;

begin
process (reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process (state, START)

begin
case state is
when s0 =>
if START = '0' then
next_state <= s1;
z <= '0';
else
next_state <= s0;
z <= '0';
end if;
when s1 =>
if START = '0' then
next_state <= s1;
z <= '0';
else
next_state <= s2;
z <= '1';
pulseCounter <= 0;
end if;
when s2 =>
if START = '0' then
next_state <= s1;
z <= '0';
else
next_state <= s0;
z <= '0';
end if;
end case;

if state = s2 and pulseCounter < 1 then

pulseCounter <= pulseCounter + 1;
else
pulseCounter <= 0;
end if;
end process;

end Behavioral;

Simulation:-

Q6. Design the data path for a serial packet receiver. (A packet is a group of bits.) The serial packet
receiver receives 256 data bits and stores them in a 64×4 RAM. After 256 bits have been received and
the RAM is full, the system asserts NewPacketReady and halts until the next Reset is asserted. The
unsynchronized SerialData input uses a code 01 to represents a “0” data bit and a code 10 to
represent a “1” data bit. The code words are presented LSB first at a rate of 1 MHz. The internal
clock of the system is 4 MHz. (Thus, on average there are 4 internal clocks per input data bit, and 2
internal clocks per input code bit.) Draw a detailed block diagram of a data path which could be used
to decode the input SerialData and fill the RAM with the data. Your block diagram should be to the
level of building blocks such as MUXes, registers, counters, shift registers, decoders, etc. List
signals which come from the data path and are input to the controller. List control signals generated
by the controlled which control the data path. Draw a timing diagram which shows all the relevant
control signals necessary for reading in the first 4 code words, storing in RAM, and updating the
RAM address. Assume that control signals are generated by a Moore type FSM running at 4 MHz.
Show as many signals as necessary. Assume the system has already received 16 bits. Design the
FSM representing the controller. Model the entire circuit using VHDL. Simulate your model to verify
the timing behavior.

Q7.Design an FSM that has an input w and an output z. The machine is a sequence detector that
produces z = 1 when the previous two values of w were 00 or 11; otherwise z = 0. Model and simulate
the FSM using VHDL.
Code:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
w : in STD_LOGIC;
z : out STD_LOGIC);
end seq_detector;

architecture Behavioral of seq_detector is

type statetype is (s0, s1, s2, s3,s4);
signal state , next_state: statetype := s0;
begin
process(reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process(state, w)
begin
case state is
when s0 =>
if w = '0' then
next_state <= s2;
z<= '0';
else
next_state <= s1;
z <= '0';
end if ;
when s1 =>
if w = '0' then
next_state <= s2;
z<= '0';
else
next_state <= s3;
z <= '0';
end if ;
when s2 =>
if w = '0' then
next_state <= s4;
z<= '0';
else
next_state <= s1;
z <= '0';
end if ;
when s3 =>
if w = '0' then
next_state <= s2;
z<= '1';
else
next_state <= s3;
z <= '1';
end if ;
when s4 =>
if w = '0' then
next_state <= s4;
z<= '1';
else
next_state <= s1;
z <= '1';
end if ;
end case;
end process ;
end Behavioral;

Simulation:-
Q8. Implement the sequence detector of problem 8 by using two FSMs. One FSM detects the
occurrence of consecutive 1s, while the other detects consecutive 0s. Model and simulate the FSM
using VHDL.
Code:- for 00 detection (overlapping case)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
w : in STD_LOGIC;
z : out STD_LOGIC);
end seq_detector;

architecture Behavioral of seq_detector is

type statetype is (s0, s1, s2);
signal state , next_state: statetype := s0;
begin
process(reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process(state, w)
begin
case state is
when s0 =>
if w = '0' then
next_state <= s1;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s1 =>
if w = '0' then
next_state <= s2;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s2 =>
if w = '0' then
next_state <= s2;
z<= '1';
else
next_state <= s0;
z <= '1';
end if ;

end case;
end process ;
end Behavioral;

Simulation:-

Code:- for 11 detection (overlapping case)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity seq_detector is
Port ( reset : in STD_LOGIC;
 clk : in STD_LOGIC;
w : in STD_LOGIC;
z : out STD_LOGIC);
end seq_detector;

architecture Behavioral of seq_detector is

type statetype is (s0, s1, s2);
signal state , next_state: statetype := s0;
begin
process(reset, clk)
begin
if reset = '1' then
state <= s0;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;

process(state, w)
begin
case state is
when s0 =>
if w = '1' then
next_state <= s1;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s1 =>
if w = '1' then
next_state <= s2;
z<= '0';
else
next_state <= s0;
z <= '0';
end if ;
when s2 =>
if w = '1' then
next_state <= s2;
z<= '1';
else
next_state <= s0;
z <= '1';
end if ;
end case;
end process ;
end Behavioral;

Simulation:-

Q9. Use functions in VHDL to model a 4X4 array multiplier.

Code:-(for 4x4 array multiplier)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Array_Mult is
port(X, Y: in bit_vector(3 downto 0);
P: out bit_vector(7 downto 0));
end Array_Mult;
architecture Behavioral of Array_Mult is
signal C1, C2, C3: bit_vector(3 downto 0);
signal S1, S2, S3: bit_vector(3 downto 0);
signal XY0, XY1, XY2, XY3: bit_vector(3 downto 0);
component FullAdder
port(X, Y, Cin: in bit;
Cout, Sum: out bit);
end component;
component HalfAdder
port(X, Y: in bit;
Cout, Sum: out bit);
end component;
function AND_Operation(X, Y: bit) return bit is
begin
return X and Y;
end function;
begin
XY0(0) <= AND_operation(X(0), Y(0));
XY1(0) <= AND_operation(X(0), Y(1));
XY0(1) <= AND_operation(X(1), Y(0));
XY1(1) <= AND_operation(X(1), Y(1));
XY0(2) <= AND_operation(X(2), Y(0));
XY1(2) <= AND_operation(X(2), Y(1));
XY0(3) <= AND_operation(X(3), Y(0));
XY1(3) <= AND_operation(X(3), Y(1));
XY2(0) <= AND_operation(X(0), Y(2));
XY3(0) <= AND_operation(X(0), Y(3));
XY2(1) <= AND_operation(X(1), Y(2));
XY3(1) <= AND_operation(X(1), Y(3));
XY2(2) <= AND_operation(X(2), Y(2));
XY3(2) <= AND_operation(X(2), Y(3));
XY2(3) <= AND_operation(X(3), Y(2));
XY3(3) <= AND_operation(X(3), Y(3));
FA1: fulladder port map (XY0(2), XY1(1), C1(0), C1(1), S1(1));
FA2: fulladder port map (XY0(3), XY1(2), C1(1), C1(2), S1(2));
FA3: fulladder port map (S1(2), XY2(1), C2(0), C2(1), S2(1));
FA4: fulladder port map (S1(3), XY2(2), C2(1), C2(2), S2(2));
FA5: fulladder port map (C1(3), XY2(3), C2(2), C2(3), S2(3));
FA6: fulladder port map (S2(2), XY3(1), C3(0), C3(1), S3(1));
FA7: fulladder port map (S2(3), XY3(2), C3(1), C3(2), S3(2));
FA8: fulladder port map (C2(3), XY3(3), C3(2), C3(3), S3(3));
HA1: HalfAdder port map (XY0(1), XY1(0), C1(0), S1(0));
HA2: HalfAdder port map (XY1(3), C1(2), C1(3), S1(3));
HA3: HalfAdder port map (S1(1), XY2(0), C2(0), S2(0));
HA4: HalfAdder port map (S2(1), XY3(0), C3(0), S3(0));
P(0) <= XY0(0); P(1) <= S1(0); P(2) <= S2(0);
P(3) <= S3(0); P(4) <= S3(1); P(5) <= S3(2);
P(6) <= S3(3); P(7) <= C3(3);
end Behavioral;

(for full adder)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
port(X, Y, Cin: in bit;
Cout, Sum: out bit);
end fulladder;
architecture df of fulladder is
begin
Sum <= X xor Y xor Cin;
Cout <= (X and Y) or (X and Cin) or (Y and Cin);
end df;

(for half adder)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HalfAdder is
port(X, Y: in bit;
Cout, Sum: out bit);
end HalfAdder;
architecture df of HalfAdder is
begin
Sum <= X xor Y;
Cout <= X and Y;
end df;

Simulation:-
Here X= 1100(12 in decimal) and Y = 1111(15 in decimal) and P = 10110100(180 in decimal)
Q10. Use functions in VHDL to model a 4 bit carry look ahead adder.
Code:- (for carry look ahead adder)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Carry_Look_Ahead is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Carry_Look_Ahead;

architecture Behavioral of Carry_Look_Ahead is

component Partial_Full_Adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end component;

signal c1,c2,c3: STD_LOGIC;

signal P,G: STD_LOGIC_VECTOR(3 downto 0);

function AND_OR(X, Y, Z: STD_LOGIC) return STD_LOGIC is

begin
return X or (Y and z);
end function;

begin

PFA1: Partial_Full_Adder port map( A(0), B(0), Cin, S(0), P(0), G(0));
PFA2: Partial_Full_Adder port map( A(1), B(1), c1, S(1), P(1), G(1));
PFA3: Partial_Full_Adder port map( A(2), B(2), c2, S(2), P(2), G(2));
PFA4: Partial_Full_Adder port map( A(3), B(3), c3, S(3), P(3), G(3));

c1 <= AND_OR(G(0),P(0), Cin);

c2 <= ( AND_OR(G(1),P(1), G(0))) OR (P(1) AND P(0) AND Cin);
c3 <= ( AND_OR(G(2),P(2),G(1))) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1) AND P(0) AND Cin);
Cout <= ( AND_OR(G(3),P(3),G(2))) OR (P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND P(1) AND
G(0)) OR (P(3) AND P(2) AND P(1) AND P(0) AND Cin);

end Behavioral;

(for partial full adder)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Partial_Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end Partial_Full_Adder;

architecture Behavioral of Partial_Full_Adder is

begin

S <= A xor B xor Cin;

P <= A xor B;
G <= A and B;

end Behavioral;

Simulation:-
At A= 0000, 1111, 1010, 1000
At B= 0000, 1111, 0111, 1001
At Cin 0, 1, 0, 0

Q11. Use functions in VHDL to model a 4 bit magnitude comparator.

Code:-
library ieee;
use ieee.std_logic_1164.all;

entity Magnitude_Comparator is
port (
A, B: in std_logic_vector(3 downto 0);
Greater, Equal, Smaller: out boolean
);
end Magnitude_Comparator;

architecture Behavioral of Magnitude_Comparator is

function GreaterThan(A, B: std_logic_vector) return boolean is
begin
return A > B;
end function;

function EqualTo(A, B: std_logic_vector) return boolean is

begin
return A = B;
end function;

function SmallerThan(A, B: std_logic_vector) return boolean is

begin
 return A < B;
end function;

begin
Greater <= GreaterThan(A, B);
Equal <= EqualTo(A, B);
Smaller <= SmallerThan(A, B);
end Behavioral;

Simulation:-
case 1:- A =1111 ,B =1100
case 2:- A= 1111 ,B =1111
case 3:- A =1010 ,B =1111