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VHDL Combinational
circuits

Dr. Hadeer A. Hosny

First term
2022-2023
2 Points to be covered:

 Conditional assignment
 With – select
 When – else
 Examples
 Concurrent Statements (Conditional
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assignment (when/else))
When/else

Relational operators
In VHDL, relational operators are used to compare two operands of the
same data type, and the received result is always of the Boolean type.
VHDL supports the following Relational Operators used in Boolean
condition:
• = Equal to
• /= Not Equal to
• < Less than
• > Greater than
 Concurrent Statements (Conditional
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assignment (With/select))

With/select

others
 Program (Multiplexer 4 x 1 Using
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When/else)
 Program (Multiplexer 4 x 1 Using
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With/Select)
 Program (Demultiplexer 1 x 4
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Using When/else)
 Program (Demultiplexer 1 x 4
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Using With/Select)
 Program (Decoder with Enable 2 x 4 Using
9 When/else )
 Program (Decoder with Enable 2 x 4 Using
10 With/Select )
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VHDL sequential circuit

 Points to be covered:
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 Combinational versus sequential circuits

 Process
 If- then
 Case
 Latch versus flip-flop
 Combinational circuit versus
13 Sequential circuit
The crucial difference between combinational and sequential circuit is
that combinational circuit result only relies on the input present at that
instant while in the sequential circuit the output of the logic not just depends
on the latest input but also on the earlier outputs.
 Process
14  PROCESS is a sequential section of VHDL code, located in
the statements part of an architecture. Inside it, only
sequential statements (IF, WAIT, LOOP, CASE) are allowed.
A simplified syntax is shown below.
 Processes Describe Sequential Behavior
 If- then
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 These statements are assignment statements to variables
that may or may not be based on a condition.
 They MUST be placed inside a process.
 If- then
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 Example if with one condition and one operation.
If a=b then com<=‘1’;
end if;

 Example if with one condition and two operations.

If a=b then com<=‘1’;
Else com<=‘0’;
end if;

 Example if with nested if.

If a=‘1’ then if a=b then com<=1;
end if;
Elsif b=‘0’ then com<=2;
End if;
 Case
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EXAMPLE:

case opcode is
when "00" => perform_add;
when "01" => perform_subtract;
when others => signal_illegal_opcode;
end case;
 Architecture

architecture mux2_arch of mux2 is

begin
mux2_1: process(a, b, sel)
begin a(7:0) 8-line
if sel = '0' then 2x1 y(7:0)
y <= a; MUX
b(7:0)
else
y <= b;
end if; sel
end process mux2_1;
end mux2_arch;
Note: <= is signal assignment
 Architecture entity name

process sensitivity list

architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin Sequential statements
if sel = '0' then (if…then…else) must be in
y <= a; a process
else
y <= b;
end if;
end process mux2_1;
end mux2_arch; Note begin…end
Note begin…end in process
in architecture
20 Latch versus flip-flop
 Latches versus flip flops
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latch

Flip flop
 VHDL code for D latch
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 23 How to Ask about Edges in
VHDL

Clk
Rising (Positive) edge Falling (Negative) edge

rising_edge (Clk) falling_edge (Clk)

or or
(Clk‘ EVENT) AND (Clk = '1‘) (Clk‘ EVENT) AND (Clk = ‘0‘)
 VHDL code for D-flip flop
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 More Control Lines
25 Clock (Clk), Reset(Rst),Enable(E)

Two types of reset:

D Q
• Positive reset
CLK
Rst = 1 Q=0 RST

• Negative reset D Q

Rstn = 0 Q=0 CLK

Rstn

These Control Lines are used in Flip-Flops, Registers & Counters.

26 Clock (Clk) + Reset(Rst) + Enable (E)
Here a problem happens when we have the three control line, which
one is executed first so we have two solutions:

Asynchronous reset
Synchronous
This means to execute Rst or E,
This means to execute Rst or the Clock must not exist first.
E, the Clock must exist first. The reset if happens so the
output =0, without checking the
clk
For example:
For example:
If rising-edge (clk) then
If Rst=‘1’ then Q =‘0’
Ask here on reset and Elsif rising-edge (clk) then
enable
Ask for enable
 D flip-flop with synchronous
27 LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY D_ff IS
PORT ( D, Rst, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END D_ff ;

ARCHITECTURE behavioral OF D_ff IS

BEGIN
PROCESS(Clk) D Q
BEGIN
IF rising_edge(CLK) THEN Clock
IF RST= '1' THEN
Reset
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END IF;
END PROCESS ;
END behavioral ;
 D flip-flop with asynchronous reset
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LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY D_ff IS
PORT ( D, RST, CLK : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END D_ff ;
ARCHITECTURE behavioral OF D_ff IS
BEGIN D Q
PROCESS (RST, CLK ) CLK
BEGIN
RST
IF RST= '1‘ THEN
Q <= '0' ;
ELSIF rising_edge(CLK) THEN
Q <= D ;
END IF ;
END PROCESS ;
END behavioral ;
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Outline of course
 Contents going to be covered during the course:
 Introduction to embedded systems, FPGA, and HDL
 VHDL basics
 VHDL for Combinational circuits
 VHDL for Sequential circuits
 AVR family and architecture.
 Learning embedded C of AVR microcontroller.
 AVR I/O
 AVR timer and counter.
 AVR communication peripherals
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