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VHDL basics and

Combinational circuits

Dr. Hadeer A. Hosny

First term
2022-2023
2 Points to be covered:

 Introduction to VHDL
 Naming and labelling
 Comments
 Libraries
 Entity
 Architecture
 Signals
 Direct assignment
 Operators
 Conditional assignment
 Introduction to VHDL

 VHDL is an acronym for VHSIC (Very High Speed

Integrated Circuit) Hardware Description Language

 IEEE standard specification language (IEEE 1076-1993) for

describing digital hardware used by industry worldwide

 VHDL enables hardware modeling from the gate level to

the system level
 Naming and Labeling
 VHDL is case insensitive
 General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and
underscore (_)
3. Do not use any punctuation or reserved characters within a
name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (__)
within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be
unique.
 Comments

Comments in VHDL are indicated with

a “double dash”, i.e., “--”
 Comment indicator can be placed anywhere in the line
 Any text that follows in the same line is treated as a comment
Example: -- This process models the state register
 Multiple line comment /* */
Example : /* This process models the state register.
It has an active low, asynchronous reset
and is synchronized on the rising edge
of the clock. */
 VHDL Code

 VHDL code is formed from 3 sections

 File extension for a VHDL file is .vhd
 Name of the file should be the same as the entity name (nand_gate.vhd)
[Coding Guidelines]
LIBRARY ieee;
USE ieee.std_logic_1164.all; LIBRARY
ENTITY nand_gate IS
DECLARATION
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
ENTITY DECLARATION
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF nand_gate IS

BEGIN
z <= a NAND b; ARCHITECTURE BODY
END model;
 Libraries IEEE (STD Logic )

Library ieee;
Use ieee.std_logic_1164.all;

Binary Standard Logic (STD_Logic)

0 0v 0 0v
1 5v 1 5v
L Weak 0
H Weak 1
U Uninitialized
- Don’t Care
X Unknown
Z High Impedance
 Libraries Arithmetic
Signed Vs. Unsigned

Use ieee.std_logic_Arith.all;
Use ieee.std_logic_Unsigned.all; OR
Use ieee.std_logic_Signed.all;

Don’t Use Both !!!

 Entity declaration
Syntax:

Entity any_name is

Port ( ------------ ;
------------ ;
------------- ) ;

End any_name ;

Example:
Entity circuit1 is
A
Port ( ------------ ; S
------------ ;
------------ ;
------------ ) ; B Co
End circuit1 ;
 Entity Inputs/Outputs
10

 External view comprises input/output signals (“ports”)

 A “port” is defined by its signal name, mode, type,
and size:
Port_name : Port mode Port-type_Port-size ;

Port Modes

In Input Pin
out Output Pin
inout Input &Output Pin
Buffer Output Pin + Storage
 Entity Inputs/Outputs
11 Port_name : Port mode Port-type_Port-size ;
Port Types
Integer Integer values 1,2,3 ….
bits Boolean 0 or 1
Std_logic Standard Logic 0, 1, L, H, -, U, Z
0 0v
1 5v
L Weak 0
Standard Logic H Weak 1
(STD_Logic) U Uninitialized
- Don’t Care
X Unknown
Z High Impedance
 Entity Inputs/Outputs
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Port_name : Port mode Port-type_Port-size ;
Port size
Single 1 wire
Vector (Buses) N wires

Vectors (Buses) are a group of wires of the same type & name,
where each wire is indexed by a number (Similar to arrays)
Std_Logic_vector ( MSB_Index downto/to LSB_Index)

Vectors Guidelines:
1- start the indices from Zero
2- Use downto if MSB_Index > LSB_Index
3- Use to if MSB_Index < LSB_Index
4- It is favorable to always use for LSB index 0 and MSB the highest
index (Vector_size -1)
 VHDL reserved keywords
13 •access •else •new •return
•after •elsif •next •select
•alias •end •nor •severity
•all •entity •not •signal
•and •exit •null •subtype
•architecture •file •of •then
•array •for •on •to
•assert •function •open •tansport
•attribute •generate •or •type
•begin •generic •others •units
•abs •guarded •out •until
•block •if •package •use
•body •in •port •variable
•buffer •inout •procedure •wait
•bus •is •process •when
•case •label •range •with
•component •library •record •xor
•configuration •linkage •register
•constant •loop •rem
•disconnect •map •report
•downto •mod
 Combinational Circuit
Example

8-line 2-to-1 Multiplexer

a(7:0)
8-line y(7:0)
b(7:0) 2 x 1 MUX

sel y
0 a
1 b
sel
 Combinational Circuit
Example

Solution using 3 methods

 An 8-line 2 x 1 MUX

a(7:0) 8-line
2x1 y(7:0)
library IEEE; MUX
b(7:0)
use IEEE.std_logic_1164.all;

entity mux2 is sel

port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
 Entity Each entity must
begin with these
library and use
statements

library IEEE;
use IEEE.std_logic_1164.all;

entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
port statement defines inputs
and outputs
 Entity

Mode: in or out
library IEEE;
use IEEE.std_logic_1164.all;

entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
Data type: STD_LOGIC,
STD_LOGIC_VECTOR(7 downto 0);
19
Architecture format
ARCHITECTURE architecture_name OF entity_name IS
-- data type definitions
-- internal signal declarations
-- component declarations
BEGIN
-- behavior of the model is described here using:
-- component instantiations
-- concurrent statements
-- processes

END architecture_name;
 VHDL Architecture Modeling
Types

1.Dataflow •The required circuit is described by means of simple

equations. (concurrent statements)

•The required circuit is described by means of already

2.Structural implemented smaller circuits. (Components and

interconnection)
•Keywords: Component, port map

•The required circuit is described by means of sequential

3.Behavioral statements. (sequential statements), it is used to describe

the behavior without hardware details.
•Keyword: Process
 Synthesis
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 Synthesis is the process of constructing a gate-level
netlist from a model of a circuit described in VHDL
22
 Signals

Signals are internal wires or buses inside the hardware that help us to
describe
23 it easier. They are defined between the Architecture & its begin

SIGNAL a : STD_LOGIC;
a
1 wire

SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);

b
8 bus
 List of VHDL Statements
24

Concurrent Statements
1) Signal Assignment
2) Conditional Assignment
3) Process Statement
4) Component Instantiation

Sequential Statements
1) Signal Assignment
2) Conditional Assignment
3) Variable Assignment
4) Loop Statements
5) Wait Statement
 Concurrent Statements (Signal
25
Assignment)
Destination & the statement output Must be of the same size

Destination <= Statement ;

Can be Statement can be

Out, Inout, or Buffer Port Direct Assignment
Signal Concatenation
Logic Operation
Can’t be Arithmetic Operation
In port
Can Have
Signals, Input, Inout , Buffers
Can’t Have
out port
 Concurrent Statements (Signal
26
Assignment (direct assignment))
 Concurrent Statements (Signal
27
Assignment (Concatenation))
 Concurrent Statements (Signal
Assignment (Shift and rotate using
concatenation))
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 (Shift Operators)
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In VHDL, shift operator is used to perform the bit
manipulation on the data by shifting and rotating the
bits of its first operand right or left.
VHDL supports the following Miscellaneous
Operators:
• Sll shift logical left
• Srl shift logical right
• Rol rotate left
• Ror rotate right
 (Shift Operators)
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Shift Left logical & Shift Right logical

<logical array> sll <integer>; --shift left logical

<logical array> srl <integer>; --shift right logical

Rotate Left and Rotate Right

<logical array> rol <integer>; --rotate left
<logical array> ror <integer>; --rotate right
 (Shift Operators)
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There are 2 methods to shift bits left in VHDL:

1. Shift Left Logical operator :

signal output : std_logic_vector ( 7 downto 0 ) ;

output <= output sll 3 ; -- Will simply pad the 3 LSB's with "000".

2. Concatenation :

signal input : std_logic ;

signal output : std_logic_vector ( 7 downto 0 ) ;
output <= output ( 6 downto 0 ) & input ;
-- Will pad the LSB with the value of input
 Concurrent Statements (Signal
32 Assignment (logic statement))
Logical Operators are used to control the program
flow. When the logical operators combined with
signals or variables, then it is used to create
combinational logic.
VHDL supports the following logical operators:
• and
• or
• nand
• nor
• xor
• xnor
• not
 Concurrent Statements (Signal
33 Assignment (arithmetic statements))

Arithmetic Operators are used to perform arithmetic

operations. These operators are numeric types, such
as integer and real.
VHDL uses the following Arithmetic Operators:
• + Addition
• - Subtraction
• * Multiplication
• / Division
34 Program
Library ieee;
Use ieee.std_logic_1164.all;

Entity HA is
Port ( A, B : in std_logic ;
S, Co : out std_logic ) ;
End HA ;

Architecture data_flow of HA is
Begin
S <= A xor B ;
Co <= A and B ;
End data_flow ;
35 Program
Library ieee;
Use ieee.std_logic_1164.all;
Entity circuit2 is
Port ( A, B, C : in std_logic ;
F1, F2 : out std_logic ) ;
End circuit2 ;
Architecture data_flow of circuit2 is
Signal X, Y, Z : std_logic ;
Begin
X <= A xor B ;
Y <= A and B ;
Z <= X and Y ;
F1 <= X xor Y ;
F2 <= (Z nand Y) nand c ;
End data_flow ;
36

Writing a VHDL program must include:

1- Hardware logic Block

(To show the inputs and the outputs names)

2- Hardware Description; any of the following if possible

Logic circuit, Truth Table, and state diagram

3- The VHDL Program

37
Outline of course
 Contents going to be covered during the course:
 Introduction to embedded systems, FPGA, and HDL
 VHDL basics
 VHDL for Combinational circuits
 VHDL for Sequential circuits
 AVR family and architecture.
 Learning embedded C of AVR microcontroller.
 AVR I/O
 AVR timer and counter.
 AVR communication peripherals
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