EE8351

DIGITAL LOGIC CIRCUITS

S.S.Harish
Department of EEE
UNIT V VHDL
Objective
To introduce digital simulation for development of application oriented logic
circuits.

• RTL Design
• combinational logic
• Sequential circuit
• Operators
• Introduction to Packages
• Subprograms
• Test bench.
• (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De
multiplexers).
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 Hardware description language (HDL)
• Manual programming of PLD- small circuit
• Large circuit- more steps and chance of flawed circuit
• Computer based design tools- reduce the risk
• Modern design uses HDL
• Describes the hardware of digital system in textual form (resembles C)
• Represent  Logic diagrams, truth table, Boolean expressions and
complex abstractions of the behaviour of digital system
• Exchange language between designers

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 Hardware description language (HDL)

Digital system modelled as

• Behavioural
• - - what is the function, eg: add
• Data flow
• --Logic equation or expression, eg: S= AB’+A’B
• Structural
• --How are interconnections to the gates made

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 Hardware description language (HDL)
Steps in design flow of an digital system (integrated circuit)
• Design entry- creates description of the functionality
• Functional simulation or verification – readable inputs and ouputs
• logic synthesis- list of physical components and interconnections(netlist)
• timing verification- after fabrication test for speed and function
• fault simulation- input that creates fault in faulty circuit

HDL

VHDL Verilog 5
 VHDL
• Very high speed integrated circuit Hardware Description Language
In VHDL “<=“ is used for = (assignment a =b)
and for AND
or for OR
after for propagation delay
VHDL is not case sensitive

VHDL program for the circuit

C<= A and B after 5 ns;
E<= C or D after 5 ns;

Concurrent statements- any change in right side re-evaluation done and updated
Order is not important 6
 VHDL

Primary constructs
• Entity declaration
• Name or function or block diagram with inputs and outputs
• Architecture body
• Internal description or interconnections
• Configuration declaration
• Package declaration
• Package body

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 VHDL
• entity – similar to function; name for what is done
• port- to define inputs and outputs
• in, out- port as input or output
• -- - comment
• Variables must start with alphabet, can contain _,numbers [_ not at end]
• Abcd1, z_1345 are valid; 1A, A2_ are invalid
• architecture- expression for the function
• begin- start of block of program lines
• end- end of block of program lines

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 VHDL
example
entity Fulladder is
port (X, Y, Cin: in bit; -- input
Cout, Sum: out bit); --output
end Fulladder;
architecture Eq of fulladder is
begin
Sum <= X xor Y xor Cin after 10 ns;
Cout <= ( X and Y) or (X and Cin) or (Y and Cin) after 10 ns;
end Eq;
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 VHDL
Operators in VHDL

Same precedence; use parenthesis

Categories operator
Logical and or nand nor xor nor
Relational = /= < >
Adding + - &
Multiplying * / mod rem
Misc Abs(absolute) ** (exponentiation)

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 VHDL
Package
• Store and share declarations
• Visible to other design units
• Package declaration and package body
Package body
package name is Hidden details of the package
Subprogram declarations
Signal declarations
File declarations
Component declarations
Attribute declarations
Attribute specification
Disconnection specification
Use clauses
end name;
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 VHDL
Subprogram
• Sequential algorithm that performs computations in zero simulation time
• 2 kinds
• Functions- used to compute single value
• Procedures- used to partition large behavioural descriptions

• Return – to main program

function vrise (signal clock_name: bit)
return Boolean is
begin
return (clock_name = ‘1’) and clock_name’event;
end vrise;

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 VHDL
Half Adder
LIBRARY ieee;
USE ieee.std logic 1164.all;
ENTITY halfadd IS
PORT (A,B: IN STD LOGIC;
Sum, Carry: OUT STD LOGIC);
END halfadd;
ARCHITECTURE logic OF halfadd IS
BEGIN
Sum <= A XOR B;
Carry <=(A AND B);
END logic;
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 VHDL
Full Adder
LIBRARY ieee;
USE ieee.std logic 1164.all;
ENTITY fulladd IS
PORT (A,B, C: IN STD LOGIC;
Sum, Carry: OUT STD LOGIC);
END fulladd;
ARCHITECTURE logic OF fulladd IS
BEGIN
Sum <= A XOR B XOR C;
Carry <=(A AND B) OR (B AND C) OR (C AND A);
END logic;

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 VHDL
Half Subtractor
LIBRARY ieee;
USE ieee.std logic 1164.all;
ENTITY halfsub IS
PORT (A,B: IN STD LOGIC;
Dif, Boro: OUT STD LOGIC);
END halfsub;
ARCHITECTURE logic OF halfsub IS
BEGIN
Dif <= A XOR B;
Boro <=(NOT A AND B);
END logic;

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 VHDL
Full Subractor
LIBRARY ieee;
USE ieee.std logic 1164.all;
ENTITY fullsub IS
PORT (A,B, C: IN STD LOGIC;
Dif, Boro: OUT STD LOGIC);
END fullsub;
ARCHITECTURE logic OF fullsub IS
BEGIN
Dif <= A XOR B XOR C;
Boro <=(NOT A AND B) OR (B AND C) OR (C AND NOT A);
END logic;

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 VHDL
Decoder
LIBRARY ieee; Data flow model
USE ieee.std logic 1164.all;
ENTITY decode2to4 IS
PORT (A,B: IN STD LOGIC;
D: OUT bit_vector(0 to 3));
END decode2to4;
ARCHITECTURE logic OF decode2to4 IS
BEGIN
D(0) <= NOT A AND NOT B;
D(1) <= NOT A AND B;
D(2) <= A AND NOT B;
D(3) <= A AND B;
END logic; 17
 VHDL
Decoder
LIBRARY ieee; Behavioural model
USE ieee.std logic 1164.all;
ENTITY decode2 IS
PORT (a: IN STD LOGIC_VECTOR(1 downto 0);
b: OUT STD LOGIC_VECTOR(3 downto 0));
END decode2;
ARCHITECTURE bhv OF decode2 IS
BEGIN
Process(a)
BEGIN
case a is
WHEN “00”=>b<=“0001”; WHEN”01” =>b<=“0010”;
WHEN “10”=>b<=“0100”; WHEN”11” =>b<=“1000”;
END case;
END process;
END bhv; 18
 VHDL
Process (sensitivity list)
Begin
• Sequential – order or flow, sequential statements
• Process- sensitivity list end
• Variables within process IF condition Then
sequential statements1;
• Signal – variable not as in or out elseif condition Then
• Signal within architecture sequential statements2;
• Inout- can be used as both input and output else
sequential statements3;
A<=b when condition end if;
Case a IS
else c when condition ; when 0=> A<=b;
else d; when condition ;
End case; 19
 VHDL
ARCHITECTURE bhv OF demux_1to4 IS
Demultiplexer BEGIN
LIBRARY ieee; process(F,S0,S1) is
USE ieee.std logic 1164.all; BEGIN
ENTITY demux_1to4 IS If (S0=‘0’ and S1=‘0’) then
PORT (F, S0, S1: IN STD LOGIC; A<=F;
Elseif (S0=‘1’ and S1=‘0’) then
A,B,C,D: OUT STD LOGIC);
B<=F;
END demux_1to4;
Elseif (S0=‘0’ and S1=‘1’) then
C<=F;
Else
D<=F;
End if;
End process;
END bhv; 20
 VHDL
ARCHITECTURE bhv OF mux_4to1 IS
Multiplexer BEGIN
LIBRARY ieee; process(A,B,C,D,S0,S1) is
USE ieee.std logic 1164.all; Begin
ENTITY mux_4to1 IS If (S0=‘0’ and S1=‘0’) then
PORT (A,B,C,D,S0,S1: IN STD LOGIC; Z<=A;
Elseif (S0=‘1’ and S1=‘0’) then
Z: OUT STD LOGIC);
Z=B;
END mux_4to1;
Elseif (S0=‘0’ and S1=‘1’) then
Z<=C;
Else
Z<=D;
End if;
End process;
END bhv; 21
 VHDL
LIBRARY ieee;
D Flip flop USE ieee.std logic 1164.all;
ENTITY dflip IS
PORT (D, clock: IN STD LOGIC;
Q: OUT STD LOGIC);
END dflip;
ARCHITECTURE bhv OF dflip IS
BEGIN
PROCESS clock
IF clock ’EVENT’ AND clock=’1’ THEN
Q<=D;
END IF;
END PROCESS;
END bhv; 22
 VHDL
ARCHITECTURE bhv OF shreg4 IS
Shift register SIGNAL sreg:STD LOGIC_VECTOR(1 TO 4);
BEGIN
LIBRARY ieee; PROCESS(clock) is
USE ieee.std logic 1164.all; BEGIN
ENTITY shreg4 IS If (CLOCK’EVENT AND clock=‘1’) then
Z<=A;
PORT (w,clock: IN STD LOGIC; Elseif (S0=‘1’ and S1=‘0’) then
Q: OUT STD LOGIC_VECTOR(1 TO 4); Z<=B;
END shreg4; Elseif (S0=‘0’ and S1=‘1’) then
Z<=C;
Else
Z<=D;
End if;
End process;
END bhv;
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 VHDL
4 bit adder ARCHITECTURE str OF ripple_adder IS
COMPONENT ful_adder_code
PORT(A,B.Cin: IN STD_LOGIC;
S, Cout: OUT STD_LOGIC);
END component;
SIGNAL c1, c2, c3: STD_LOGIC;
BEGIN
Structural model FA1:full_adder_code PORT MAP(A(0), B(0), Cin, S(0), c1);
LIBRARY IEEE; FA2:full_adder_code PORT MAP(A(1), B(1), Cin, S(1), c2);
USE IEEE.STD_LOGIC_1164.ALL; FA3:full_adder_code PORT MAP(A(2), B(2), Cin, S(2), c3);
ENTITY ripple_adder IS FA4:full_adder_code PORT MAP(A(3), B(3), Cin, S(3), Cout);
PORT (A: IN STD_LOGIC_Vector(3 downto 0); END str;
B: IN STD_LOGIC_Vector(3 downto 0);
Cin: IN STD_LOGIC;
S: OUT STD_LOGIC_VECTOR(3 downto 0);
Cout: OUT STD_LOGIC);
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END ripple_adder;
 VHDL
Asynchronous counter ARCHITECTURE bhv OF count4 IS
SIGNAL count: STD_LOGIC_VECTOR(3 downto 0);
BEGIN
LIBRARY IEEE; PROCESS( clock, Resetn)
USE IEEE.STD_LOGIC_1164.ALL; BEGIN
ENTITY count4 IS IF Resetn=’0’ THEN
PORT (Resetn: IN STD_LOGIC; Cout<=”0000”;
B, clock: IN STD_LOGIC; ELSEIF(clock’EVENT AND Clock_’1’) THEN
Q: OUT STD_LOGIC_VECTOR(3 IF B=’1’ THEN
downto 0); Count<=Count+1;
END count4; END IF;
END IF;
END PROCESS;
Q<=Count;
END bhv;

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 VHDL

Structural model

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 VHDL
MOORE MODEL

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 BEGIN

VHDL PROCESS( clock, Resetn)

BEGIN
IF Resetn=’0’ THEN
y<=A;

MOORE MODEL ELSEIF(Clock’EVENT AND Clock=’1’) THEN

CASE y IS
WHEN A=>
LIBRARY IEEE; IF w=’0’ THEN
USE IEEE.STD_LOGIC_1164.ALL; y<= A;
ENTITY moore IS ELSE
y<=B;
PORT (Clock: IN STD_LOGIC;
END IF;
w, clock: IN STD_LOGIC; WHEN B=>
Resetn: IN STD_LOGIC; IF w=’0’ THEN
z: OUT STD_LOGIC); y<= A;
ELSE
END moore; y<=C;
ARCHITECTURE bhv OF moore IS END IF;
TYPE State type IS (A,B,C); WHEN C=>
IF W=’0’ THEN
SIGNAL y: State type;
y<= A;
SIGNAL count: STD_LOGIC_VECTOR(3 downto 0); ELSE
y<=B;
END IF;
END CASE;
END IF;
END PROCESS;
z<=’1’ WHEN y=C ELSE ‘0’; 28
END BHV;
 VHDL
Test bench
• Environment used to verify
correctness of the design
• Software and hardware
• Non-synthesizable
• Documented, repeatable
set of stimuli

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 Course outcome
• VHDL
• Operators
• Package
• Subprogram
• Test bench
• Behavioural model
• Dataflow model
• Structural model
• Adder, Subtractor, multiplexer, demultiplexer, decoder, flipflop,
counter, shift register,
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 Objectives
• To study various number systems and simplify the logical expressions
using Boolean functions
• To study combinational circuits
• To design various synchronous and asynchronous circuits.
• To introduce asynchronous sequential circuits and PLDs
• To introduce digital simulation for development of application
oriented logic circuits.

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 Course outcome
Unit 1:
Unit 4:
• Number systems, arthimetic operations, 2’s • Asynchronous circuit- propagation delay
compliment • Hazards & errors
• Binary codes, (Gray, Excess-3, BCD, Parity, Hamming) • Programmable logic devices- PROM, PAL,
• Digital logic families –RTL,DTL,TTL,ECL,MOS,CMOS PLA, CPLD, FPGA

Unit 2:
Boolean expression forms- Canonical, SOP, POS-
Simplification using theorems and K-map
Adder, Subtractor, multiplexer, demultiplexer,
encoder, decoder, code converter
Unit 3:
Latch, Flipflop- SR, JK, D, T
Counter, Shift register,
FSM –Moore, Mealy model, State assignment,
State reduction
Unit 5:
• VHDL- operators, package, sub program
• Behavioural, data flow, structural
• Adder, Subtractor, multiplexer,
demultiplexer, decoder, flipflop, counter,
shift register
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 Unit 4

• Algorithmic
state machine

• Asynchronous
circuit model

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