Course Code: EEE 426/ ETE 448

Course Title: VLSI I/ VLSI DESIGN LAB

Experiment No: 8
Experiment Name: Introduction to Hardware Description Language (HDL) and
EDA Playground

OBJECTIVE:

The objective of this experiment is to get familiar with the grammar and coding technique of
Verilog in a commercial simulator.
THEORY:

HDL: A hardware description language (HDL) is a programming language used to describe the
behavioror structure of digital circuits (ICs). HDLs are also used to simulate the circuit and check
its response. It means, that by using an HDL we can describe any digital hardware at any level.
Designs, which are described in HDL are independent of technology, very easy for designing and
debugging, and are normally more useful than schematics, particularly for large circuits. Many
HDLs are available, but VHDL and Verilog are by far the most popular. Verilog is a language used
for describing a digital system like a network switch or a microprocessor or a memory or a
flip−flop.

Verilog: Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used

for describing a digital system like a network switch or a microprocessor or a memory or a
flip−flop. It means, that by using an HDL we can describe any digital hardware at any level.
Applied to electronic design, Verilog is intended to be used for verification through simulation,
timing analysis, test analysis (testability analysis and fault grading), and logic synthesis. Even more
basic understanding of electrical energy and also complete knowledge of electrical components
such as inductors, capacitors, resistors, and their mathematical behavior is required for a VLSI
design engineer.

Types of Verilog Coding:

1. Behavioral:
➢ Procedural code, similar to C programming
➢ Little structural detail (except module interconnect)
2. Dataflow
➢ Specifies transfer of data between registers
 ➢ Some structural information is available (RTL)
➢ Sometimes similar to behavior
3. Structural (gate, switch)
➢ Interconnection of simple components
➢ Purely structural

DUT (Device Under Test)

• Represents Hardware
• Usually RTL or GTL

Testbench
• Represents System
• Usually Behavioral
• Using higher order languages (“e”/SystemVerilog)

How do you write codes in Verilog?

1. Introduction.
2. Data Types.
3. Building Blocks. Verilog assign statements. Verilog assign examples.
4. Behavioral modeling. Verilog for Loop. Verilog case Statement.
5. Gate/Switch modeling. User-Defined Primitives.
6. Simulation. Verilog Clock Generator.
7. System Tasks and Functions. Verilog Math Functions. Verilog Timeformat

EDA Playground: EDA Playground is a free online application that enables users to modify,
simulate (and see) their HDL code, synthesize it, and share it. Its objective is to expedite design
and testbench development learning by facilitating code sharing and simplifying access to
simulators and libraries.

Elements of Verilog:

Logic Values
0 zero, logic low, false, ground
1 one, logic high, power
X unknown
Z high impedance, unconnected, tri-state

Data Types Declaration Remakrs

Nets wire [<range>] <net_name> ; physical connections between devices
Registers reg [<range>] <reg_name>; Implicit storage-holds its value until a new
value is assigned to it
Parameters They are not variables, they are constants
 Numbers <size>’<radix> <value> Size: No. of bits
Radix: b (Binary), o (Octal), h (Hexadecimal), d
(Decimal)
Value: 0-9, A-F, X (don’t care)

Gate Primitives: and, or, not, buf, xor, nand, nor, xnor, bufif1, bufif0m notif1, notif0

Operators
Logical AND &&
Logical OR ||
Logical NOT !
Bitwise AND &
Bitwise OR |
Bitwise NOT ~
Bitwise XOR ^
Bitwise XNOR ~^
Shift Right >>
Shift Left <<

Keywords:

module, endmodule, input, output, inout, reg, integer, real, time, not, and, nand, or, nor, xor,
parameter, begin, end, fork, join, specify, endspecify

Types of Verilog Coding:

1. Behavioral:
• Procedural code, similar to C programming
• Little structural detail (except module interconnect)

2. Dataflow
• Specifies transfer of data between registers
• Some structural information is available (RTL)
• Sometimes similar to behavior

3. Structural (gate, switch)

• Interconnection of simple components
• Purely structural

Structure of Verilog code:

module my_module (out1, .., inN);

output out1, .., outM;
input in1, .., inN;

.. // declarations
.. // description of f (maybe
.. // sequential)

endmodule
 PROCEDURE:

1. Go to https://www.edaplayground.com/ .
2. Log in to the web simulator using an institutional email address.
3. Select Icarus Verilog 0.9.7 as a simulator from the “ Tools and Simulators” on the left
4. If you want to display the wave (i.e activated dumpfile) : Click “Open EPWave after run”
on the left sidebar under “Tools and Simulators”
5. Write the code in testbench and design.sv and simulate it in the simulator.

Example:

1. Inverter

design.sv

module inverter(out, A);

output out;
input A;

assign out = ~A;

endmodule

testbench.sv

module testbench1();
reg A1;
wire out1;
inverter your_name (out1, A1);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);

A1 = 0; #1;
$display("Output: %b",out1);
A1 = 1; #1;
$display("Output: %b",out1);

end
endmodule

2. Timing diagram from edaplayground

REPORT:

1. Write Verilog code for OR, AND, NOR, and NAND Gate in the simulator.

REFERENCE:

• Fundamentals of Digital Logic (3rd Edition) by S. Brown and Z. Vranesic, Mcgraw – Hill
Companies.

Prepared by:
Md. Zesun Ahmed Mia
Lecturer,
Department of EEE, ULAB.
Spring 2021

Assisted by:
Samia Howlader (181016023), TA, Spring 22