Introduction to Verilog HDL

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 Digital Systems Design
• HDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost and
time
– avoid design errors!

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 Modeling Digital Systems
• HDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost and
time
– avoid design errors!

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Generation of ICs

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IC Design Flow

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Hardware Description Languages
• HDL can be used to describe any digital
system:
• For example, a computer or a component.
• A digital system can be described at several
levels:
• Switch level: wires, resistors and transistors
• Gate level: logic gates and flip flops
• Register Transfer Level (RTL): registers and
the transfers of information between registers.
 Introduction to Verilog
• Verilog is Hardware description language(HDL).
• It describes digital system like MP, FF, Registers, Memory etc.
• HDL descriptions provide technology-independent documentation of
a design and its functionality.
• Design style :
→ Bottom-up -- Each design is performed at gate level
→ Top Down -- Desired style of all designers- early testing is done.
Basic Limitation of HDL
Description of digital systems only
 Application Areas of HDL
System Specification
Suitable for all levels
Behavioral level
Not suitable
HW/SW
Partition

Hardware Softwre
Spec Spec

ASIC

FPGA Boards
Software
&
PLD Systems

Std Parts
 Abstraction Levels in HDLs

Behavioral

RTL Our focus

Gate

Layout (VLSI)
 Why use HDL? 1
• When HDL was first developed:
▪Most logic simulators operated on
netlists
• Netlist:
▪List of gates and how they’re
connected
▪A natural representation of a digital
logic circuit
• Not a very convenient way to
express designs, simulate, debug… 11
 Why use HDL? 2
• Text-based
• Allows simulation before building
circuit
• Can be compiled (synthesized)
into logic circuit
• Much easier to write test
benches
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 Why use HDL? 3
• More abstract models of circuits
▪Easier to write
▪Simulates faster
• More flexible
• Provides sequencing
• A major par of Verilog’s success:
▪It allowed both the model and the
testbench to be described together
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 Two Major HDLs
• VHDL
• Verilog HDL
• Virtually every chip (FPGA, ASIC,
etc.):
▪ Designed in part using one of these
two languages
• Combines structural and behavioral
modeling styles. 14
 VHDL
• “V” is short for Very High Speed
Integrated Circuits.
• Designed for and sponsored by US
Department of Defense.
• Designed by a committee (1981-1985).
• Syntax based on Ada programming
language.
• Was made an IEEE Standard in 1987.
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 Verilog HDL
• Introduced in 1985 by Gateway
Design System Corporation:
▪ Now a part of Cadence Design
Systems, Inc.
• Became an IEEE Standard in 1995
• Syntax based on C programming
language.
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 Verilog Compared to VHDL
• VHDL
▪ Provides some high-level constructs
not available in Verilog:
• E.g. user defined types, configurations
• Verilog
▪ Provides comprehensive support for
low-level digital design.
▪ Not available in native VHDL
• E.g. Range of type definitions and
supporting functions (called packages). 17
 Verilog Compared to VHDL
• Verilog and VHDL are comparable languages
• VHDL has a slightly wider scope
▪ System-level modeling
▪ Fewer sources of nondeterminism (e.g., no
shared variables)
• VHDL is harder to simulate quickly
• VHDL has fewer built-in facilities for
hardware modelling
• VHDL is a much more verbose language
▪ Most examples don’t fit on slides
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Design Methodology

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 Two Main Components of
Verilog
• Behavior
▪Concurrent, event-triggered
processes
• Structure:
▪Wires, interconnection, etc.

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 Structural vs. Behaviorial
Verilog
• Structural verilog:
▪ Module instances and their
interconnections (by wires) only.
• Behavioral verilog:
▪ The use of regs, explicit time
delays, arithmetic expressions,
procedural assignments, and other
verilog control flow structures.
 Concept of Verilog “Module”
• In Verilog, the basic unit of hardware
is called a module.
▪ Modules cannot contain definitions of
other modules.
▪ A module can, however, instantiate
another module.
▪ Allows the creation of a hierarchy in a
Verilog description.
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 Basic Syntax of Module
Definition
module module_name (list_of_ports);
input/output declarations
local net declarations
Parallel statements
endmodule

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Example 1 :: Simple AND
gate

module simpleand (f, x, y);

input x, y;
output f;
assign f = x & y;
endmodule

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Concept of Verilog “Module”

• In Verilog, the basic unit of hardware is called a module.

module module_name (list_of_ports);

input/output declarations;

local net declarations;

parallel statements;

endmodule
Example 1 :: simple AND gate

module simpleand (f, x, y);

input x, y;
output f;
assign f = x & y;
endmodule
Example 2 :: two-level circuit

module two_level (a, b, c, d, f);

input a, b, c, d;
output f;
wire t1, t2;
assign t1 = a & b;
assign t2 = (c | d);
assign f = t1 ^ t2;
endmodule
Variable Data Types

• A variable belongs to one of two data types:

–Net
• Must be continuously driven
• Used to model connections between continuous
assignments & instantiations
–Register
•Retains the last value assigned to it
•Often used to represent storage elements
Net data type

– Different ‘net’ types supported for synthesis:

– wire, supply0, supply1

– ‘supply0’ / ‘supply1’ model power supply connections.

Register data type

–Different ‘register’ types supported for synthesis:

reg, integer

–The ‘reg’ declaration explicitly specifies the size.

reg x, y; // single-bit register variables
reg [15:0] bus; // 16-bit bus, bus[15] MSB

–For ‘integer’, it takes the default size, usually 32-bits

Other differences:
–In arithmetic expressions,
• An ‘integer’ is treated as a signed quantity.
• A ‘reg’ is treated as an unsigned quantity.

–General rule of thumb

• ‘reg’ used to model actual hardware registers such as
counters, accumulator, etc.
• ‘integer’ used for situations like loop counting.
Specifying Constant Values

A value may be specified in either the ‘sized’ or the ‘un-sized’

form.
Syntax for ‘sized’ form:
<size>’ <base> <number>
•Examples:
8’b01110011 // 8-bit binary number
12’hA2D // 12-bit hexadecimal number
1’b0 // Logic 0
1’b1 // Logic 1
Primitive Gates

• Primitive logic gates (instantiations):

• and G (out, in1, in2);
• nand G (out, in1, in2);
• or G (out, in1, in2);
• nor G (out, in1, in2);
• xor G (out, in1, in2);
• xnor G (out, in1, in2);
• not G (out1, in);
• buf G (out1, in);
Verilog Operators

• Arithmetic operators
*, /, +, -, %
• Logical operators
! logical negation
&& logical AND
|| logical OR
• Relational operators
>, <, >=, <=, ==, !=
• Bitwise operators
~, &, |, ^, ~^
• Shift operators
>>, <<
• Conditional
<condition> ? <expression1> : <expression2>
Description Styles in Verilog

• Three different styles of description:

1.Gate Level
• Gate Level assignment
2.Data flow
• Continuous assignment
3.Behavioral
• Procedural assignment
Gate Level Modeling

• Logic gates can be used to design logic circuits

• Basic Logic gates defined by Verilog – Primitives

• Not, And, Or, Xor, Xnor, Buf

• Examples
module generate_sum (a, b, c);
input a, b;
output c;
xor (c, a, b);
endmodule
Data-flow Modeling

• Identified by the keyword “assign”.

assign a = b & c;
assign f[2] = c[0];

• The assignment is continuously active.

• Almost exclusively used to model combinational logic.

module generate_sum (a, b, c);
input a, b;
output c;
assign c = a+b;
endmodule
Behavioral Modeling

• The procedural block defines

–A region of code containing sequential statements.
• Two types of procedural blocks in Verilog
–The “always” block
•A continuous loop that never terminates.
–The “initial” block
•Executed once at the beginning of simulation (used in
Test-benches).