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Digital System Design

Subject Code : 18CS3IOT01
Total Hours : 45
Credits : 03
Branch : Internet of Things
Semester :3
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RECAP
• INTRODUCTION TO SHIFT REGISTERS
• APPLICATIONS
• TYPES OF SHIFT REGISTERS
• SISO, SIPO, PISO, PIPO
• BI-DIRECTIONAL SHIFT REGISTER
• UNIVERSAL SHIFT REGISTER
• COUNTERS: ASYNCHRONOUS AND SYNCHRONOUS
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Topics of the Session
• Introduction to HDL
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Why HDL:

• Hardware Description Language is a language that describes the

hardware of digital systems in a textual form.

• It is s programming language

• The main difference with the traditional programming languages

is
HDL’s representation of extensive concurrent operations whereas
traditional ones represents mostly sequentially operations.
• The most common use of a HDL is to provide an alternative to
schematics.
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HDL:

• Structural description in which the language describes an

interconnection of components.

• Such a structural description can be used as input to logic

simulation just as a schematic is used.

• Models for each of the primitive components are required.

• If an HDL is used, then these models can also be written in the

HDL providing a more uniform, portable representation for
simulation input
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» Self Assessment Question

1. What is the HDL……

a. Concurrent

b. Sequential

c. Both a and b

d. None of the above

• Answer: C
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» Self Assessment Question

• 2. HDL is…..

a. Hardware Description Language

b. Hardware Description Level

c. Hard-core Description Language

d. None of the above

• Answer: a
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» Self Assessment Question

3. Which of the following describe hardware?

a. C

b. C++

c. Java

d. HDL

• Answer: d
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» HDL:

• HDL can be used for:

• Logic diagrams,

• Boolean expressions,

• other more complex digital circuits.

• Top down design is a very high-level description of a entire

system that can be precisely specified using an HDL
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• As a documentation language, HDL is used to represent and
document digital systems in a form that can be read by both
humans and computers

• The language content can be stored and retrieved easily and

processed by computer software in an efficient manner.

• There are two applications of HDL processing: Simulation and

Synthesis
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• Hardware description languages (HDL)
– Language to describe hardware
– Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description Language
– Developed by DOD from 1983
– IEEE Standard 1076-1987/1993/200x
– Based on the ADA language
• Verilog
– IEEE Standard 1364-1995/2001/2005
– Based on the C language
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Applications of HDL
• Model and document digital systems
– Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
– Convert from higher abstraction levels to lower abstraction levels
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» Simulation:

• A simulator interprets the HDL description and produces a

readable output

 Timing diagram, that predicts how the hardware will behave

before its is actually fabricated.

• Simulation allows the detection of functional errors in a design

without having to physically create the circuit.
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» Simulation:

» The stimulus that tests the functionality of the design is called a test
bench.
» To simulate a digital system and design is was first described in HDL
having verified by simulating the design and checking it with a test
bench which is also written in HDL.
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» Describing a Design:

• In VHDL an entity is used to describe a hardware module.

• An entity can be described using

• Entity declaration

• Architecture
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» Entity Declaration:

• It defines the names, input output signals and modes of a hardware

module.

• Syntax −
entity entity_name is
Port declaration;
end entity_name;
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» Entity Declaration:

• An entity declaration should start with ‘entity’ and end with ‘end’
keywords. The direction will be input, output or inout.
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» Self Assessment Question

• 4. What does an entity specify in the VHDL program format?

a. List of all libraries associated with the design

b. Code properties of VHDL

c. Input/output pins of the circuit

d. The behaviour of circuit

• Answer: c
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» Architecture:

• Architecture can be described using structural, dataflow,

behavioral or mixed style.
• Syntax −

architecture architecture_name of entity_name

architecture_declarative_part;

begin
Statements;
end architecture_name;
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Input-Output specification of circuit
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VHDL Architecture
• architecture arch_name of my_ckt
is
begin
p1: process (A,B,S)
• begin
if (S=‘0’) then
X <= A;
else
X <= B;
end if;
end process p1;
end;
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DIFFERENT MODELLING STYLES IN VHDL
1. BEHAVIORAL
2. DATA-FLOW
3. STRUCTURAL
4. MIXED
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Dataflow Style of Modelling:
• Dataflow style describes a system in terms of how data flows through the
system. Data dependencies in the description match those in a typical
hardware implementation.
• A dataflow description directly implies a corresponding gate-level
implementation.
• Dataflow descriptions consist of one or more concurrent signal assignment
statements
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Data Flow style of Half-Adder Description
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• The first assignment statement describes how input data flows from
inputs a and b through an XOR function to create sum.
• The second assignment statement describes how input data flows through
an AND function to produce carry_out.
• Anytime there is an event on either input, the statements concurrently
compute an updated value for each output.
• The concurrent signal assignment statements in this description directly
imply a hardware implementation consisting of an XOR gate and an
AND gate.
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Behavioral Style of Modelling
• A Behavioural description describes a system’s behavior or function in an
algorithmic fashion.
• Behavioural style is the most abstract style. The description is abstract in
the sense that it does not directly imply a particular gate-level
implementation.
• Behavioural style consists of one or more process statements. Each
process statement is a single concurrent statement that itself contains one
or more sequential statements.
• Sequential statements are executed sequentially by a simulator, the same
as the execution of sequential statements in a conventional programming
language.
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Behavioral Style of Modelling
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• The entity declaration is the same as for the dataflow architecture.
However, the architecture body is quite different. This architecture consists
of a single process statement.
• The process statement starts with the label ha followed by the keyword
process. A label on a process is optional, but is useful to differentiate
processes in designs that contain multiple processes.
• Following the keyword process is a list of signals in parentheses, called a
sensitivity list. A sensitivity list enumerates exactly which signals cause
the process to be executed. Whenever there is an event on a signal in a
process’s sensitivity list, the process is executed.
• Between the second begin keyword and the keywords end process is a
sequential if statement. This if statement is executed whenever the process
executes.
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Structural Style of Data Modelling
• In structural style of modelling, an entity is described as a set of
interconnected components.
• The top-level design entity’s architecture describes the interconnection of
lower-level design entities. Each lower-level design entity can, in turn, be
described as an interconnection of design entities at the next-lower level,
and so on.
• Structural style is most useful and efficient when a complex system is
described as an interconnection of moderately complex design entities.
This approach allows each design entity to be independently designed and
verified before being used in the higher-level description.
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• The half adder is described as an interconnection of an XOR gate design entity
and an AND gate design entity.
• Design entity half_adder describes how the XOR gate and the AND gate are
connected to implement a half adder. It is this top-level entity that has a
structural style description.
• In VHDL, a component is actually a placeholder for a design entity. A structural
design that uses components simply specifies the interconnection of the
components.
• When components are used, each must be declared. A component declaration is
similar to an entity declaration in that it provides a listing of the component’s
name and its ports. Component declarations start with the keyword component.
• A port map tells how a design entity is connected in the enclosing architecture.
• In the statement part of the half-adder architecture are two component
instantiation statements. Each one creates an instance(copy) of a design entity.
Component instantiation statements require unique labels.
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VHDL Code for Full-Adder:

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);

end full_adder;

architecture data of full_adder is

begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;
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VHDL Code for Half-Subtractor:

Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;

architecture data of half_sub is

begin
d<= a xor c;
b<= (a and (not c));
end data;
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VHDL Code for Full-Subtractor:

Library ieee;
use ieee.std_logic_1164.all;

entity full_sub is
port(a,b,c:in bit; sub,borrow:out bit);
end full_sub;

architecture data of full_sub is

begin
sub<= a xor b xor c;
borrow <= ((b xor c) and (not a)) or (b and c);
end data;
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VHDL Code for Multiplexer:
Library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;

architecture data of mux is

begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;
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VHDL Code for De-multiplexer:
Library ieee;
use ieee.std_logic_1164.all;

entity demux is
port(S1,S0,D:in bit; Y0,Y1,Y2,Y3:out bit);
end demux;

architecture data of demux is

begin
Y0<= ((Not S0) and (Not S1) and D);
Y1<= ((Not S0) and S1 and D);
Y2<= (S0 and (Not S1) and D);
Y3<= (S0 and S1 and D);
end data;
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BEHAVIORAL MODEELING
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Frequently Asked Questions