SEMINAR REPORT ON

 VHSIC HARDWARE DESCRIPTION LANGUAGE

(VHDL)
 
 
 

CREATED BY:
KAUSTUBH KIRTI
2K7/EE/837
DELHI TECHNOLOGICAL UNIVERSITY
kaustubhkirti@gmail.com
 CONTENTS
• Introduction
• History
• Basic Components
• Design Units
• Entity Declaration
• Architecture Modeling
• Structural Modeling
• Dataflow Modeling
• Behavioral Modeling
• Advantages & Capabilities
• Conclusion
• References
 INTRODUCTION
• An HDL is any language from a class of computer
languages, specification languages, or modeling
languages for formal description and design of
electronic circuits, and most-commonly, digital logic.
• Modeling digital circuits 
• VHDL is industry standard in digital circuit modeling
• Now also used in programmable devices according to
desired need
 HISTORY
• VHSIC was a 1980s U.S. government program to develop very-high-speed
integrated circuits. The United States Department of Defense launched
the VHSIC project in 1980. To program it they created a language VHDL
• At that time a serious requirement of a common language. There was a
dire need to standardize the entire system for usage. Answer to the
problem???? VHDL
• A team of three companies IBM, Texas Instruments and Intermetrics were
awarded the contract by the Department of Defense to develop a version
of the language in 1983. It was finally released for the public in the year
1985.
 BASIC COMPONENTS
• ENTITY - All designs are
expressed in terms of
entities. An entity is the
most basic building block in
a design
• ARCHITECTURE - . The
architecture describes the
behavior of the entity.
• CONFIGURATION - A
configuration statement is
used to bind a component
instance to an entity-
architecture pair.
How to do we model digital
system??
 DESIGN UNITS
• Entity Declaration
• Architecture Body
1. Structural Style of
Modeling
2. Behavioral Style of
Modeling
3. Dataflow Style of
Modeling
 Entity Declaration
• A hardware abstraction of the
digital system is called entity.
• This declaration specifies the
names of the ports being
modeled and the set of
interface ports

entity HALF_ADDER is
port(A,B: in BIT; S,C: out BIT);
end HALF_ADDER;
2-to-4 decoder circuit
• Input ports (A,B,INP)
• Output ports – we have specified an array
Z(0)-Z(3)

entity DECODER2X4 is
port(A,B,INP: in BIT; Z: out BIT_VECTOR(0 to
3));
end DECODER2X4;
 Architecture Modeling

architecture DATAFLOW of HALF_ADDDER is

begin
S<= A xor B;
C<= A and B;
end dataflow;
 Structural Modeling
Structural Style of Modeling
 
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X,Y: in BIT; Z: out BIT);
end component
component AND2
port (L,M: in Bit; N: out BIT);
end component;
begin
X1:XOR2 port map (A, B, S);
A1:AND2 port map (A, B, C);
end HA_STRUCTURE;
 
• The architecture here is composed of two parts namely the declarative
part and the statement part.

• The declaration specifies the interface of the components that are used in
the architecture body. The components XOR2 and AND2 a either be
predefined components in a library or if they do not exist they may later
be put as components.
 Dataflow Style of Modeling
For the DECODER 2X4 entity, we have
 
architecture DEC_DATAFLOW of DECODER2X4
is
signal ABAR,BBAR: BIT;
begin
OUT(3)<= not (A and B and INP);
OUT(0)<= not (ABAR and BBAR and INP);
BBAR<= not B;
OUT(2)<= not (A and BBAR and INP);
ABAR<=not A;
OUT(1)<= not (ABAR and B and INP);
end DEC_DATAFLOW;
• We are making use of the flow of data.
• Discreet values of the system are not considered. Henceforth the concept
of signal has come into the picture.
 Behavioral Style of Modeling
architecture DEC_SEQUENTIAL of DECODER2X4 is
begin
process (A,B,INP)
variable ABAR, BBAR: BIT;
begin
ABAR:= not A;
BBAR:=not B;
if In=’1’ then
OUT(3)<= not (A and B);
OUT(0)<= not (ABAR and BBAR);
OUT(2)<= not (A and BBAR);
OUT(1)<= not (ABAR and B);
else
OUT<=”1111”;
end if;
end process;
end DEC_SEQUENTIAL;
• Here ABAR and BBAR are not signals as they are given values and not
continuous waveforms. That is the main difference between dataflow and
behavioral style of modeling.
• This set of sequential statements which are specified inside a program, do
not explicitly specify the structure but provide a basic backdrop for its
working.
 ADVANTAGES & CAPABILITIES
• The principal advantage of VDHL as a language is standardization.
 
• Another key capability of the VHDL is that it allows the entire system to be
described and verified and modeled through simple coding. This helps in
pre determining the functioning of the devices and validity of the circuit
we have designed.
 
• The language supports hierarchy that is a digital system can be modeled
as a set of interconnected components; each component in turn can be
modeled as a set of interconnected subcomponents.
 
• The device is used to program devices like FPGA. The hardware
description that VHDL provides is extremely simple and helps in
construction of the complex systems very easily.
 
• Another benefit is that VHDL allows the description of a concurrent
system. VHDL is a dataflow language, unlike procedural computing
languages such as BASIC, C, and assembly code, which all run sequentially,
one instruction at a time.
 
 CONCLUSION
VHDL after its introduction to the public in 1985 it has
standardized the HDL market. Every chip producer now
focuses on configuring devices based on VHDL. Another
important substitute of VHDL is Verilog. VHDL has also
played an important part in pre determining the function
of complex circuit be programming. It has all led to an
efficient development of a number of digital circuits. Also
VHDL is special is because it deals with signals. It is not
dependent of particular values at a particular time. It
incorporates a parallel setup.
 REFERENCES
 
[1] A VHDL Primer, Third Edition J. Bhasker, Bell Laboratories, Lucent technologies Allentown, PA.
[2] IEEE P1076 / VHDL Analysis and Standardization Group (VASG),
http://www.eda.org/vhdl-200x/
[3] VHDL:Programming by Example,
Douglas L. Perry, Fourth Edition, McGraw-Hill
[4] http://vhdlguru.blogspot.com/
[5] http://en.wikipedia.org/wiki/VHDL
[6] seas.upenn.edu/ese171/vhl/vhdl_primer.html, Jan Van der Spiegel, University of Pennsylvania,
Department of Electrical and Systems Engineering
[7] http://www.doulos.com/knowhow/vhdl_
designers_guide/