PAMANTASAN NG CABUYAO

COLLEGE OF COMPUTING AND ENGINEERING

COURSE CODE: CPP 110

COURSE DESCRIPTION: INTRODUCTION TO HDL

COURSE INTENDED On the completion of the course, student is expected to be able to do the
LEARNING OUTCOMES: following:

1. The ability to code and simulate any digital function in HDL.

2. Understand library modeling, behavioral code and the differences
between them.
3. Understand the differences between simulator algorithms as well
as Logic verification using HDL software tool
4. Learn good coding techniques per current industrial practices

LEARNING MATERIAL FOR 1

WEEK NUMBER:

I. TITLE: Introduction to HDL

II. OBJECTIVES: By the end of this module you should be able to:

1. Gain familiarity on HDL field

2. Understand complexity of evolving electronics gearing to FPGA
3. Understand top-down and bottom-up design methodologies for
digital design.

III. INTRODUCTION:
The purpose of this module is to introduce what High Definition Language
is. The module discusses the digital logic design evolution and therefore
the basic ASIC design flow. It describes the need of ASIC SOC prototype.

The comparison of ASIC and FPGA implementation is described in these

sub-topics. This module is helpful to the HDL beginners to grasp about
the difference between problem-oriented language and HDL modeling
styles.

IV. CONTENTS:

Lesson Coverage:

- Introduction to High Definition Language

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HIGH DEFINITION LANGUAGE (HDL)

Evolution of Computer Aided Digital Design

Digital circuit design has evolved rapidly over the last 25 years. The earliest digital circuits were designed with
vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on one chip.

The first computer circuit (IC) chips were SS1 (Small Scale Integration) chips where the gate count was very
small. As technologies became sophisticated, designers were able to place circuits with many gates on a chip.
These chips were called MS1 (Medium Scale Integration) chips. With the arrival of LSI (Large Scale Integration),
designers could put thousands of gates on one chip.

At now, design processes started getting very complicated, and designers felt the requirement to automate these
processes. Computer Aided Design (CAD)' techniques began to evolve. Chip designers began to use circuit and
logic simulation techniques to verify the functionality of building blocks of the order of about 100 transistors.

The circuits were still tested on the breadboard, and also the layout was done on paper or by hand on a graphic
computer terminal. With the arrival of VLSI (Very Large Scale Integration) technology, designers could design
single chips with quite 100,000 transistors. due to the complexity of those circuits, it absolutely was unacceptable
to verify these circuits on a breadboard.

Computer-aided techniques became critical for verification and style of VLSI digital circuits.

Computer programs to try and do automatic placement and routing of circuit layouts also became popular. The
designers were now building gate-level digital circuits manually on graphic terminals. they'd build small building
blocks then derive higher-level blocks from them.

What is Hardware Schematics?

A hardware schematic is a diagram that shows hoe the combinational gates should be connected to achieve a
particular hardware functionality. In this case, it is the set of NAND gates connected towards the left. However,
if we know what values of inputs contribute to make the output have a value of 1, then we can essentially hide
the internal details of the connections and encapsulate it into a black box. This block provides us with certain
inputs and outputs that is similar to the hardware schematic made up of combinational gates.

Combinational NAND and NOR

https://www.chipverify.com/verilog/verilog-introduction

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Hardware Description Language

Emergence of HDLs

For a protracted time, programming languages like FORTRAN, Pascal, and C were getting used to explain
computer programs that were sequential in nature. Similarly, within the digital design field, designers felt the
necessity for a regular language to explain digital circuits.

Thus, Hardware Description Languages (HDLs) came into existence. HDLs allowed the designers to model the
concurrency of processes found in hardware elements.

Hardware description languages like Verilog HDL and VHDL became popular. Verilog HDL originated in 1983
at Gateway Design Automation. Later, VHDL was developed under contract from DARPA. Both verilogB and
VHDL simulators to simulate large digital circuits quickly gained acceptance from designers.

Digital circuits can be described at a register transfer level (RTL) by use of an HDL. Thus, the looker had to
specify how the information flows between registers and the way the design processes the info. The details of
gates and their interconnections to implement the circuit were automatically extracted by logic synthesis tools
from the RTL description.

Typical Design Flow

A typical design flow for designing VLSI IC circuits is shown in Figure. Unshaded blocks show the extent of
design representation; shaded blocks show processes within the design flow.

In any design, specifications are written first. Specifications describe

abstractly the functionality, interface, and overall architecture of the
digital circuit to be designed.

At this time, the architects don't must consider how they will implement
this circuit. A behavioral description is then created to investigate the
planning in terms of functionality, performance, compliance to standards,
and other high-level issues. Behavioral descriptions may be written with
HDLs.

ASIC Design Flow (Courtesy: Verilog HDL by Samir Palnitkar)

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Importance of HDL

1. HDLs have many advantages compared to traditional schematic-based design. Designs is described at a
really abstract level by use of HDLs. Designers can write their RTL description without choosing a
particular fabrication technology.

Logic synthesis tools can automatically convert the planning to any fabrication technology. If a
replacement technology emerges, designers don't have to redesign their circuit. They simply input the
RTL description to the logic synthesis tool and make a brand new gate-level netlist, using the new
fabrication technology.

The logic synthesis tool will optimize the circuit in area and timing for the new technology.
2. By describing designs in HDLs, functional verification of the look is done early within the design cycle.
Since designers work the RTL level, they will optimize and modify the RTL description until it meets the
required functionality.

Most design bugs are eliminated at this time. This cuts down design cycle time significantly because the
probability of hitting a functional bug at a later time within the gate-level netlist or physical layout is
minimized.
3. Designing with HDLs is analogous to programming. A textual description with comments is a better
thanks to develop and debug circuits. This also provides a concise representation of the planning,
compared to gatelevel schematics. Gate-level schematics are almost incomprehensible for very complex
designs.

Popularity of Verilog HDL

Verilog HDL has evolved as a standard hardware description language. Verilog HDL offers many useful features
for hardware design. Verilog HDL is a general-purpose hardware description language that is easy to learn and
easy to use. It is similar in syntax to the C programming language. Designers with C programming experience
will find it easy to learn Verilog HDL.

Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a
hardware model in terms of switches, gates, RTL, or behavioral code. Also, a designer needs to learn only one
language for stimulus and hierarchical design. Most popular logic synthesis tools support Verilog HDL. This
makes it the language of choice for designers.

All fabrication vendors provide Verilog HDL libraries for postlogic synthesis simulation. Thus, designing a chip
in Verilog HDL allows the widest choice of vendors.

The Programming Language Interface (PLI) is a powerful feature that allows the user to write custom C code to
interact with the internal data structures of Verilog. Designers can customize a Verilog HDL simulator to their
needs with the PLI.

Trends in HDLs

The speed and complexity of digital circuits has increased rapidly. Designers have responded by designing at
higher levels of abstraction. Designers must think only in terms of functionality. CAD tools be sure of the
implementation details.

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With designer assistance, CAD tools became sophisticated enough to try and do a close-to-optimum
implementation. The most popular trend currently is to style in HDL at an RTL level, because logic synthesis
tools can create gate-level netlists from RTL level design.

Behavioral synthesis has recently emerged. As these tools improve, designers will be able to design directly in
terms of algorithms and also the behavior of the circuit, and then use CAD tools to try to to the interpretation and
optimization in each phase of the design. Behavioral modeling are going to be used more and more as behavioral
synthesis matures. Until then, RTL design will remain highly regarded.

Formal verification techniques are appearing on the horizon. Formal verification applies formal mathematical
techniques to verify the correctness of Verilog HDL descriptions and to ascertain equivalency between RTL and
gate level netlists. However, the requirement to explain a design in Verilog HDL won't go away.

For very high speed and timing-critical circuits like microprocessors, the gate level netlist provided by logic
synthesis tools isn't optimal. In such cases, designers often mix gate-level description directly into the RTL
description to achieve optimum results.

This practice is opposite to the high-level design paradigm, yet it's frequently used for high-speed designs because
designers need to squeeze the last little bit of timing out of circuits and CAD tools sometimes sway be insufficient
to realize the required results.

A trend that's emerging for system-level design could be a mixed bottom-up methodology where the designers
use either existing Verilog HDL modules, basic building blocks, or vendor-supplied core blocks to quickly point
out their system simulation.

Before we discuss the main points of the Verilog language, we must first understand basic hierarchical modeling
concepts in digital design. The designer must use a "good" design methodology to try and do efficient Verilog
HDL based design.

In this we discuss typical design methodologies and illustrate how these concepts are translated to Verilog. A
digital simulation is formed from various components. We discuss the components and their interconnections.

Design Methodologies

There are two basic sorts of digital design methodologies: a top-down design methodology and a bottom-up
design methodology.

In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to create
the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that can't
further be divided.

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Figure 2 Top-down Design Methodology

In a bottom-up design methodology, we first identify the

building blocks that are available to us. We build bigger cells,
using these building blocks.

These cells are then used for higher-level blocks until we build
the top-level block within the design.

https://irreni.blogspot.com/2015/08/you-need-to-start-making-
political.html

Figure 2 shows the top-down design process.

Figure 2-1 Bottom-up Design Methodology

Typically, a combination of top-down and bottom-up flows is used.

Design architects define the specifications of the top-level block. Logic
designers decide how the design should be structured by breaking up the
functionality into blocks and sub-blocks.

At the same time, circuit designers are designing optimized circuits for
leaf-level cells. They build higher-level cells by using these leaf cells.

The flow meets at an intermediate point where the switch-level circuit

designers have created a library of leaf cells by using switches, and the
logic level designers have designed from top-down until all modules are
defined in terms of leaf cells

https://irreni.blogspot.com/2015/08/you-need-to-start-making-
political.html

Levels of Abstraction

Verilog language has the aptitude of designing a module in several coding styles. betting on the requirements of
a design, internals of every module are often defined at four level of abstractions. regardless of the inner
abstraction level, the module would behave exactly within the similar thanks to the external environment.

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Following are the four different levels of abstraction which may be described by four different coding sorts of
Verilog language:

• Behavioral or Algorithmic level

• Dataflow level
• Gate level or Structural level
• Switch level

The order of abstraction mentioned above are from highest to lowest level of abstraction.

Verilog is both a behavioral and a structural language. Internals of every module will be defined at four levels of
abstraction, betting on the wants of the planning.

The module behaves identically with the external environment regardless of the amount of abstraction at which
the module is described.

The internals of the module are hidden from the environment. Thus, the amount of abstraction to explain a module
may be changed with none change within the environment. The levels are defined below.

Behavioral or algorithmic level

This is the very best level of abstraction provided by Verilog HDL. A module may be implemented in terms of
the specified design algorithm without worrying for the hardware implementation details. Designing at this level
is extremely almost like C programming.

Dataflow level

At this level the module is intended by specifying the information flow. The designer is attentive to how data
flows between hardware registers and the way the information is processed within the design.

Gate level

The module is implemented in terms of logic gates and interconnections between these gates. Design at this level
is analogous to describing a design in terms of a gate-level logical diagram.

Switch level

This is the bottom level of abstraction provided by Verilog. A module may be implemented in terms of switches,
storage nodes, and also the interconnections between them. Design at this level requires knowledge of switch-
level implementation details.

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Verilog allows the designer to combine and match all four levels of abstractions in an exceedingly design. within
the digital design community, the term register transfer level (RTL) is usually used for a Verilog description that
uses a mix of behavioral and dataflow constructs and is appropriate to logic synthesis tools.

If a design contains four modules, Verilog allows each of the modules to be written at a special level of abstraction.
because the design matures, most modules are replaced with gate-level implementations.

Normally, the upper the amount of abstraction, the more flexible and technology independent the planning. joined
goes lower toward switch-level design, the planning becomes technology dependent and inflexible. A little
modification can cause a major number of changes within the design.

Modules

We now relate these hierarchical modeling concepts to Verilog. Verilog provides the concept of a module. A
module is that the basic building block in Verilog.

A module may be part or a set of lower-level design blocks. Typically, elements are grouped into modules to
supply common functionality that's used at many places within the design.

A module provides the required functionality to the higher-level block through its port interface (inputs and
outputs), but hides the interior implementation. this enables the looker to switch module internals without
affecting the remainder of the design.

In Verilog, a module is said by the keyword module. A corresponding keyword endmodule must appear at the
top of the module definition.

Each module must have a module-name, which is that the identifier for the module, and a module-terminal-list,
which describes the input and output terminals of the module.

Syntax Module Declaration Module Sample

Specifically, the T-flipflop could be defined as a

module as follows:
SYNTAX FOR MODULE

module T-FF (q, clock, reset) ;

module <module-name> (<module-terminal-
list>) ;

<functionality of T-flipflop>

<module internals>

... endmodule

endmodule

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MODULE the basic building block of Verilog which is followed by the name of the design . The body of the
design is enclosed inside the module, and the module is ended by endmodule.

Instantiation

A module provides a template from which you can create actual objects. When a module is invoked, Verilog
creates a unique object from the template. Each object has its own name, variables, parameters and 1/0 interface.
The process of creating objects from a module template is called instantiation, and the objects are called
instances.

The word instantiation means to transfer. Transfer => transfer the property of the design. It is a process to create
an object for the Design which will replicate it’s all property where it is instantiated.

module Ripple_carry_counter(clk,rst,q); LEGEND

input clk,rst; q[0], rst, clk - PORT LIST

output[3:0] q; tff0 - Instance name

T_FF tff0 ( q[0], rst, clk ); T_FF - Instantiation

endmodule

Instantiation Methods

There are two methods of Instantiation they are :

• Name Based
• Ordered Based

Example:

// an example of a half adder verilog code.

module half_adder( S, C, A, B); // module name and port declaration
output S; // output port declaration
output C; // output port declaration

input A; // input port declaration

input B; // input port declaration

xor x1(S, A, B); // instantiation of xor gate

and a1(C, A, B); // instantiation of and gate

endmodule

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NAME BASED

//Full Adder Verilog Code

module Full_adder(SUM, Cout, P, Q, Cin);

output SUM, Cout; //output port
input P, Q, Cin; //input port

wire S1, Co1, Co2;

half_adder H1 ( .S1(S), .Co1(C), .P(A), .Q(B) ) //ports are connected by
half_adder H2 ( .SUM(S), Co2(C), .S1(A), .Cin(B) ); // name to each signal
or o1(Cout, Co1, Co2);
Endmodule //module half_adder( S, C, A, B)

ORDERED BASED

//Full Adder Verilog Code

module Full_adder(SUM, Cout, P, Q, Cin);

output SUM, Cout; //output port
input P, Q, Cin; //input port

wire S1, Co1, Co2;

half_adder H1 ( S1, Co1(C), .P(A), .Q(B) ) //ports are connected by
half_adder H2 ( SUM, Co2, S1,Cin ); // name to each signal
or o1(Cout, Co1, Co2);
Endmodule //module half_adder( S, C, A, B)

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V. REFERENCES: Roth, C.H. Jr. And John, L. K. (2018). Digital Systems Design Using VHDL (3rd
ed.). Texas, USA: Cengage Unlimited

Brown, S. and Vranesic, Z. (2009). Fundamentals of Digital Logic with VHDL

Design. (3rd ed.). New York, NY: McGraw-Hill

Online Readings and Guide

Hardware Description Language | VLSI Tutorial | Mepits

VHDL || Electronics Tutorial (electronics-tutorial.net)

Index of /ece232/pdf (umass.edu)

VI. ASSESSMENT TASK:

See Attached file given by the instructor

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