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(Assistant Lecturer)
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DIGITAL SYSTEM DESIGN FLOW AND
HARDWARE DESCRIPTION LANGUAGES
(HDLS)
INTRODUCTION
Traditionally, digital system design was a manual process of
designing and capturing circuits using schematic entry tools.
This process has many disadvantages and is rapidly being
replaced by new methods.
System designers are always competing to build cost-
effective products as fast as possible in highly competitive
environment.
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INTRODUCTION
In order to achieve this, top down design methodologies
including Hardware Description Languages (HDLs) and
synthesis and simulation are in use.
ASIC
Non-channeled/channel-less
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ASIC AND FPGA DEVICES
Standard Cell
In this category devices do not have the concept of a cell
and no components are prefabricated on the silicon chip.
The manufacturer creates custom masks for every stage of
device’s process and means silicon is utilized much more
efficiently than gate arrays.
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ASIC AND FPGA DEVICES
FPGAs
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ASIC AND FPGA DEVICES
FPGAs
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
The main difference with the traditional programming
languages is HDL’s representation of extensive parallel
operations whereas traditional ones represent mostly serial
operations.
The most common use of a HDL is to provide an
alternative to schematics.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
HDL can be used to represent logic diagrams, Boolean
expressions, and other more complex digital circuits.
Thus, in top down design, a very high-level description of
a entire system can be precisely specified using an HDL.
This high-level description can then be refined and
partitioned into lower-level descriptions as a part of the
design process.
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HARDWARE DESCRIPTION
LANGUAGES (HDL)
There are two standard HDL’s that are supported by IEEE.
VHDL (Very-High-Speed Integrated Circuits Hardware
Description Language) - Sometimes referred to as
VHSIC HDL, this was developed from an initiative by
US. Dept. of Defense.
Verilog HDL – developed by Cadence Data systems and
later transferred to a consortium called Open Verilog
International (OVI). 15
HDL BASED DIGITAL DESIGN
Why HDLs?
Support larger system designs.
By describing the design in a high-level (=easy to
understand) language, we can simulate our design
before we manufacture it. This allows us to catch
design errors.
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HDL TOOL SUITES
Text editor
Allows you to write, edit and save an HDL program.
Compiler
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HDL TOOL SUITES
Synthesizer
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HDL TOOL SUITES
Simulator
Schematic viewer
Creates schematic diagram corresponding to an HDL
program, based on output of compiler.
May differ from final synthesized result.
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HDL TOOL SUITES
Translator
Back annotator
Inserts delay clauses or statements in the original HDL
source program, corresponding to delays calculated by the
timing analyzer. 23
HDL –BASED DESIGN FLOW
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FRONT-END STEPS
Block diagram: define modules and their interfaces
Coding: writing of HDL code for modules, their
interfaces and their internal details
Compilation: the HDL compiler analyzes the code for
syntax errors and compatibility with other modules on
which it relies
Simulation: define and apply inputs to the design and
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observe its outputs.
FRONT-END STEPS
Verification:
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BACK-END STEPS
Synthesis: converts the HDL description into a set of
primitives or components that can be assembled in the
target technology.
E.g.: with PLDs and CPLDs, the synthesis tool may
generate two-level SOP equations.
With ASICs, it may generate a list of gates and a netlist
that specifies how they should be connected
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BACK-END STEPS
Fitting: a fitter maps the synthesized primitives or
components onto available device resources.
For PLD or CPLD, this means assigning equations to
available AND-OR elements.
For FPGA or ASIC, it means selecting macro-cells or
laying down individual gates in a pattern and finding
ways to connect them within the physical constraints of
the FPGA or ASIC die--- place-and-route process 28
BACK-END STEPS
Timing verification: actual circuit delays due to wire
lengths, electrical loading and other factors can be
calculated with reasonable precision
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THANK YOU!!!!!!!!!!
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