1.

SYLLABUS
Subject code:15ECL58 IA marks:20
No. of practicalHrs. /week:03 Exam hours:03
Total no. of practicalHrs.42 Exam marks:80.
…………………………………………………………………………
(ACCORDING TO VTU SYLLABUS)
PART – A

PROGRAMMING (using VHDL and Verilog)

1.Write Verilog code to realize all thegates.

2.Write a Verilog program for the following combinationaldesigns

a). 2 to 4decoder
b). 8 to 3 (encoder without priority & with priority)
c). 8 to 1 multiplexer
d). 4 bit binary to gray converter
e). Multiplexer, de-multiplexer,comparator.

3. Write a HDL code to describe the functions of a full adder using three modelingstyles.
4. Write a model for 32 bit ALU using the schematic diagram shown belowA(31:0)

• ALU should use the combinational logic to calculate an output based on thefour
bit op-code input.
• ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
• ALU should decode the 4 bit op-code according to the given in examplebelow.

5. Develop theVerilog code for the following flip-flops SR, D, JK &T.

6. Design 4 bit binary, BCD counters (Synchronous reset and asynchronous reset) and “any
sequence”counters Using Verilog code.
PART - B

INTERFACING (at least four of the following must be covered using VHDL/Verilog)

1. Write HDL code to display messages on an alpha numeric LCD display.

2. Write HDL code to interface Hex key pad and display the key code on seven segment display.

3. Write HDL code to control speed, direction of DC and stepper motor.

4. Write HDL code to accept 8 channel analog signal, Temperature sensors and display the data on
LC panel or seven segment display

5. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using
DAC change the frequency and amplitude.

6. Write HDL code to simulate Elevator operation

 2. OVERVIEW OF HDL LAB

2.1 HDL
In electronics, a hardware description language or HDL is any language from a class of
Computer languages for formal description of electronic circuits. It can describe the circuit's
operation, its design and organization, and tests to verify its operation by means of simulation
HDLs are standard text-based expressions of the spatial, temporal structure and behavior of
electronic systems. In contrast to a software programming language, HDL syntax, semantics
include explicit notations for expressing time and concurrency, which are the attributes of
hardware. Languages whose only characteristic is to express circuit connectivity between a
hierarchies of blocks are properly classified as netlist languages.
HDLs are used to write executable specifications of some piece of hardware. A simulation
program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the
ability to model a piece of hardware before it is created physically. It is this execute ability
that gives HDLs the illusion of being programming languages. Simulators capable of supporting
discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.
It is certainly possible to represent hardware semantics using traditional programming languages
such as C++, although to function such programs must be augmented with extensive and
unwieldy class libraries. Primarily, however, software programming languages function as a
hardware description language
Using the proper subset of virtually any language, a software program called a
synthesizer can infer hardware logic operations from the language statements and produce an
equivalent netlist of generic hardware primitives to implement the specified behavior. This
typically requiresthesynthesizertoignoretheexpressionofanytimingconstructsinthetext.

The two most widely-used and well-supported HDL varieties used in industry are
 VHDL (VHSICHDL)
 Verilog
2.2 VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is
commonly used as a design-entry language for field-programmable gate arrays and application-
specific integrated circuits in electronic design automation of digital circuits.
VHDL is a fairly general-purpose language, and it doesn’t require a simulator on which to run
the code. There are a lot of VHDL compilers, which build executable binaries. It can read and
write files on the host computer, so a VHDL program can be written that generates another
VHDL program to be incorporated in the design being developed. Because of this general-
purpose nature, it is possible to use VHDL to write a test bench that verifies with the user,
and compares results with those expected. This is similar to the capabilities of the Verilog
language
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as
Xilinx or Quartus) to produce the RTL schematic of the desired circuit. After that, the
generated schematic can be verified using simulation software (such as ModelSim) which
shows the waveforms of inputs and outputs of the circuit after generating the appropriate
test bench. To generate an appropriate test bench for a particular circuit or VHDL code,
the inputs have to be defined correctly. For example, for clock input, a loop process or an
iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). When a VHDL model is
translated into the "gates and wires" that are mapped onto a programmable logic device such
as a CPLD or FPGA, then it is the actual hardware being configured, rather than the
VHDLcode being"executed"as if on some form of aprocessor chip.
Both VHDL and Verilog emerged as the dominant HDLs in the electronics industry while
older and less-capable HDLs gradually disappeared from use. But VHDL and Verilog share
many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit
simulation. Neither possesses language constructs to describe recursively-generated logic
structures
2.3 Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed -
signal circuits at various levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming
language so that it would be familiar to engineers and readily accepted. The language is case-
sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"
and "while", are similar. The formatting mechanism in the printing routines and language
operators and their precedence are also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces
to define a block of code. The concept of time, so important to a HDL won't be found in C The
language differs from a conventional programming language in that the execution of statements
is not strictly sequential. A Verilog design consists of a hierarchy of modules are defined
with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires
and registers. Concurrent and sequential statements define the behavior of the module by
defining the relationships between the ports, wires, and registers Sequential statements are
placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel,
qualifying Verilog as a Dataflow language. A module can also contain one or more instances
of another module to define sub-behavior
A subset of statements in the language is synthesizable. If the modules in a design contains a
netlist that describes the basic components and connections to be implemented in hardware only
synthesizable statements, software can be used to transform or synthesize the design into the net
list may then be transformed into, for example, a form describing the standard cells of an
integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).

Describing a design
In VHDL an entity is used to describe a hardware module
An entity can be described using,
1. Entity declaration
2. Architecture.
1. Entity declaration
It defines the names, input output signals and modes of a hardware module
Syntax
Entity entity _ name is
port declaration
end entity name

An entity declaration should start with “entity” and ends with “end” keywords. Ports are
interfaces through which an entity can communicate with its environment. Each port must have a
name, direction and a type. An entity may have no port declaration also. The direction will be
input, output or inout.

2. Architecture:
It describes the internal description of design or it tells what is there inside design
each entity has at least one architecture and an entity can have many architectures.
Architecture can be described using structural, dataflow, behavioral or mixed style.

Syntax:
architecture architecture_name of entity_name is
architecture_declarative_part;
begin
statements;
endarchitecture_name;
Here we should specify the entity name for which we are writing the architecture body. The
architecture statements should be inside the begin and end keyword. Architecture declarative part
may contain variables, constants, or component declaration.
The internal working of an entity can be defined using different modeling styles inside
architecture body. They are

 Data flowmodeling
 Behavioral modeling
 Structural modeling.

Structure of an entity:

 Dataflow modeling
In this style of modeling, the internal working of an entity can be implemented using
concurrent signal assignment.
Consider a half adder as an example which is having one XOR gate and a AND gate as shown
below
Program

Here STD_LOGIC_1164 is an IEEE standard which defines a nine-value logic type, called
STD_ULOGIC. Use is a keyword, which imports all the declarations from this package. The
architecture body consists of concurrent signal assignments, which describes the functionality of
the design. Whenever there is a change in RHS, the expression is evaluated and the value is
assigned to LHS.

Behavioral modeling:
In this style of modeling, the internal working of an entity can be implemented using set of
statements.
It contains:
Process
Statements,
Sequential
statements and

Signal assignment statements

Process statement is the primary mechanism used to model the behavior of an entity it
contains sequential statements, variable assignment (:=) statements or signal assignment
(<=) statements etc. It may or may not contain sensitivity list. If there is an event occurs on any
of the signals in the sensitivity list, the statements within the process are executed. Inside the
process the execution of statements will be sequential and if one entity is having two
processes the execution of these processes will be concurrent. At the end it waits for another
event to occur.

Here whenever there is a change in the value of A OR B the process statements are executed.
Structural modeling
The implementation of an entity is done through set of interconnected components. It
contains
Signal declaration.
Component instances
Port maps.
Wait statements.
Component declaration:
Syntax:
Component Component_name
List_of_interface ports;
end component component_ name;
Before instantiating the component it should be declared using component declaration as
shown above. Component declaration declares the name of the entity and interface of a
component.

Consider the example of full adder using 2 half adder and 1 OR gate.

Schematic Diagram of full adder

The program written for half adder in dataflow modeling is instantiated as shown above.
HA is the name of the entity in dataflow modeling. C1, C2, S1 are the signals used for internal
connections of the component which are declared using the keyword signal. Port map is used to
connectdifferentcomponentsaswellasconnectcomponentstoportsoftheentity.

Component instantiation is done as follows.

Component_label: component_name port map (signal_list);

Signal list is the architecture signals which will be connected to component ports. This can be
done in different ways. What is declared above is positional binding. One more type is the named
binding.
The above can be written as,
HA1: ha port map (A => A, B => B, S => S1, C => C1);
HA2: ha port map (A => S1, B => Cin, S=> SUM, C => C2);
2.4 Design usingHDL
The vast majority of modern digital circuit design revolves around an HDL
description of the desired circuit, device ,or subsystem.
Most designs begin as a written set of requirements or a high-level architectural diagram.
The process of writing the HDL description is highly dependent on the designer's diagram.
The process of writing the HDL description is highly dependent on the designer's
background and the circuit's nature. The HDL is merely the 'capture language'–often begin
with a high-level algorithmic description such as MATLAB or a C++ mathematical model
Control and decision structures are often prototyped in flowchart applications, or entered in a
state-diagram editor. Designers even use scripting languages (such as PERL) to automatically
generate repetitive circuit structures in the HDL language. Advanced text editors (such as
PERL) to automatically generate repetitive circuit structures in the HDL language. Advanced
text editors (such as Emacs) offer editor templates for automatic indentation, syntax-
dependent coloration, and macro-based expansion of entity/architecture/signal declaration.
As the design's implementation is fleshed out, the HDL code invariably must undergo code
review, or auditing. In preparation for synthesis, the HDL description is subject to an array
of automated checkers. The checkers enforce standardized code guidelines, identifying
ambiguous code construct before they can cause misinterpretation by downstream synthesis, and
check for common logical coding errors, such as dangling ports or shorted outputs.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis
tool has mapped the HDL description into a gate net list, this net list is passed off to the back -
end stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-
cell), HDLs may or may not play a significant role in the back-end flow. In general, as the
design flow progresses toward a physically realizable form, the design database becomes
progressively more laden with technology-specific information, which cannot be becomes
progressively more laden with technology-specific information, which cannot be stored in a
generic HDL- description. Finally, a silicon chip is manufactured in a fab.
 2.5 Simulating and debugging HDLcode
Essential to HDL design is the ability to simulate HDL programs. Simulation allows a HDL description of a
design (called a model) to pass design verification, an important milestone that validates the design's
intended function (specification) against the code implementation in the HDL description. It also permits
architectural exploration. The engineer can experiment with design choices by writing multiple variations of
a base design, then comparingtheirbehaviorinsimulation.Thus,simulationiscriticalforsuccessfulHDLdesign
To simulate an HDL model, an engineer writes a top-level simulation environment (called a test
bench). At minimum, a test bench contains an instantiation of the model (called the device under test or
DUT), pin/signal declarations for the model's I/O, and a clock waveform. An HDL simulator–the
program that executes the test bench–maintains the simulator clock, which is the master reference for all
events in the test bench simulation Events occur only at the instants dictated by the test bench
HDL, or in reaction to stimulus and triggering events.

Design verification is often the most time-consuming portion of the design process, due to the
disconnect between a device's functional specification, the designer's interpretation of the specification,
and the imprecision of the HDL language. The majority of the initial test/debug cycle is conducted in
the HDL simulator environment, as the early stage of the design is subject to frequent and major circuit
changes. An HDL description can also be prototyped and tested in hardware–programmable logic devices
are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL
simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing
against other hardware devices, and hardware prototypes, even those running on slow FPGAs, offer
much faster simulation times than pure HDL simulation.
PART-A
EXPERIMENT No: 1 Write a Verilog code to realize all the logic gates.

Objectives:
 Study the HDL code to realize all the logic gates.
 Simulate and synthesize the HDL code of all the logic gates.

1a. ALL BASIC GATES

SYMBOLS AND TRUTH TABLES OF ALL BASIC GATES

VERILOG

module and1(andout,orout,nandout,norout,xorout,xnorout,notout,a,b);
input a,b;
output andout,orout,nandout,norout,xorout,xnorout,notout;
assign andout= a&b;
assign orout = a|b;
assign notout = ~a;
assign nandout = ~(a&b);
assign norout = ~(a|b);
assign xorout = a^b;
assign xnorout = ~(a^b);
endmodule
RTL Schematic

Waveform

Truth Table
a b andout orout xorout xnorout nandout norout not out
0 0 0 0 0 1 1 1 1
0 1 0 1 1 0 1 0 1
1 0 0 1 1 0 1 0 0
1 1 1 1 0 1 0 0 0

Generic Skills / Outcomes:

 Identify the gate symbols for the Boolean operations AND, OR, NOT and XOR.
 Construct a table with the input/output behavior of each individual gate.

Result:
EXPERIMENT N0:2. Write a Verilog program for the following combinational designs

a. 2 to 4 decoder b. 8 to 3 (encoder without priority & with priority)

c. 8 to 1 multiplexer d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
Objectives:
 Study about the decoder, encoder, multiplexer and convertors.
 Simulate and synthesize the codes for decoder, encoder, multiplexer and
convertors.

2a. 2:4 DECODER

RTL Schematic

TRUTH TABLE

En Din(1) Din(0) Dout(3) Dout(2) Dout(1) Dout(0)

1 x x 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0

VERILOG

module decoder2_4v(en,Din,Dout);
input en;
input [1:0] Din;
output [3:0] Dout;
reg [3:0] Dout;
always @(reset,Din)
begin
if (en==1'b1)
begin
Dout=4'b0000;
end
else
begin
case(Din)
2'b00 : Dout=4'b0001;
2'b01 : Dout=4'b0010;
2'b10 : Dout=4'b0100;
2'b11 : Dout=4'b1000;
endcase
end
end
endmodule

SIMULATION RESULT

Result:

2b(1). 8:3 ENCODER(WITHOUT PRIORITY)

RTL Schematic

TRUTH TABLE
INPUTS OUTPUTS
reset din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout(2) dout(1) dout(0)
1 X x x x x x x x 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1

VERILOG

module encoder8_3v(din,reset,dout);
input [7:0] din;
input reset;
output [2:0] dout;
reg [2:0] dout;
always @(din,reset)
begin
if (reset == 1'b1)
dout = 3'b000;
else
begin
case (din)
8'b00000001 : dout=3'b000;
8'b00000010 : dout=3'b001;
8'b00000100 : dout=3'b010;
8'b00001000 : dout=3'b011;
8'b00010000 : dout=3'b100;
8'b00100000 : dout=3'b101;
8'b01000000 : dout=3'b110;
8'b10000000 : dout=3'b111;
default : dout=3'b000;
endcase
end
end
endmodule

SIMULATION RESULT
2b(2).8:3 ENCODER(WITH PRIORITY)

RTL Schematic

TRUTH TABLE
INPUTS OUTPUTS
reset din(7) din(6) din(5) din(4) din(3) din(2) din(1) din(0) dout(2) dout(1) dout(0)
1 x x x x x x x x 0 0 0
0 x x x x x x x 1 0 0 0
0 x x x x x x 1 0 0 0 1
0 x x x x x 1 0 0 0 1 0
0 x x x x 1 0 0 0 0 1 1
0 x x x 1 0 0 0 0 1 0 0
0 x x 1 0 0 0 0 0 1 0 1
0 x 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1

VERILOG

module encoder8_3v(din,reset,dout);
input [7:0] din;
input reset;
output [2:0] dout;
reg [2:0] dout;
always @(din,reset)
begin
if (reset == 1'b1)
dout = 3'b000;
else
begin
casex (din)
8'bxxxxxxx1 : dout= 3'b000;
8'bxxxxxx10 : dout = 3'b001;
8'bxxxxx100 : dout = 3'b010;
8'bxxxx1000 : dout = 3'b011;
8'bxxx10000 : dout = 3'b100;
8'bxx100000 : dout = 3'b101;
8'bx1000000 : dout = 3'b110;
8'b10000000 : dout = 3'b111;
default : dout =3'b000;
endcase
end
end
endmodule

SIMULATION RESULT

Result

2c. 8:1 MULTIPLEXER

RTL Schematic

TRUTH TABLE

S(2) S(1) S(0) Z

0 0 0 i(0)
0 0 1 i(1)
0 1 0 i(2)
0 1 1 i(3)
1 0 0 i(4)
1 0 1 i(5)
1 1 0 i(6)
1 1 1 i(7)

VERILOG

module mux(i,s,z);
input [7:0] i;
input [2:0] s;
output z;
reg z;
always@(i,s)
begin
case(s)
3'b000:z=i[0];
3'b001:z=i[1];
3'b010:z=i[2];
3'b011:z=i[3];
3'b100:z=i[4];
3'b101:z=i[5];
3'b110:z=i[6];
3'b111:z=i[7];
Default:z=1’b0;
endcase
end
endmodule

SIMULATION RESULT

Result:

2d(1). BINARY TO GRAY CONVERTER

RTL Schematic
VERILOG
module bintogray(b,g);
input [3:0] b;
output [3:0] g;
reg [3:0] g;
always@(b)
begin
g[3]=b[3];
g[2]=b[3] ^ b[2];
g[1]=b[2] ^ b[1];
g[0]=b[1] ^ b[0];
end
endmodule

SIMULATION RESULT

2e(1). 4:1 MULTIPLEXER

RTL Schematic

TRUTH TABLE

Sel(1) Sel(0) Output Y

0 0 Y(0)
0 1 Y(1)
1 0 Y(2)
1 1 Y(3)
VERILOG
module mux41(i,s,y);
input [3:0] i;
input [1:0] s;
output y;
assign y=(~(s[1])&(~(s[0]))& i[0])|(~(s[1])& s[0]& i[1])|(~(s[0])& s[1]& i[2])|(s[1]& s[0]& i[3]);
endmodule

SIMULATION RESULT

Result:

2e(2). 1:4 DE-MULTIPLEXER

RTL Schematic

TRUTH TABLE

Sel(1:0) y(0) y(1) y(2) y(3)

00 a 0 0 0
01 0 a 0 0
10 0 0 a 0
11 0 0 0 a
VERILOG

module demux(a,s,y);
input a;
input [1:0] s;
output [3:0] y;
assign y[0]=(a&(~(s[1]))&(~(s[0])));
assign y[1]=(a&(~(s[1]))&s[0]);
assign y[2]=(a&(~(s[0]))&s[1]);
assign y[3]=(a&s[1]&s[0]);
endmodule

SIMULATION RESULT

Result:

2f. 1:8 DE-MULTIPLEXER

RTL Schematic
TRUTH TABLE

Input Output
reset Sel d(7) d(6) d(6) d(4) d(3) d(2) d(1) d(0)
210
1 xxx 0 0 0 0 0 0 0 0
0 000 0 0 0 0 0 0 0 y
0 001 0 0 0 0 0 0 Y 0
0 010 0 0 Y 0 0 Y 0 0
0 011 0 0 0 0 y 0 0 0
0 100 0 0 0 y 0 0 0 0
0 101 0 0 Y 0 0 0 0 0
0 110 0 Y 0 0 0 0 0 0
0 111 y 0 0 0 0 0 0 0

VERILOG
module demux1_8(reset,y,sel,d);
input y;
input reset;
input [2:0] sel;
output [7:0] d;
reg [7:0] d;
always@(sel,y,reset)
begin
if(reset==1'b1)
d=8'b00000000;
else
begin
case (sel)
3'b000 : d[0] = y ;
3'b001 : d[1] = y ;
3'b010 : d[2] = y ;
3'b011 : d[3] = y ;
3'b100 : d[4] = y ;
3'b101 : d[5] = y ;
3'b110 : d[6] = y ;
3'b111 : d[7] = y ;
default :d=8’b0;
end
endcase
end
end
endmodule
SIMULATION RESULT

Result:

2g. COMPARATOR

RTL Schematic

Verilog Code

module compverilog(a,b, q1,q2,q3,q4,);

input [3:0] a,b;
output q1,q2,q3,q4;
reg q1,q2,q3,q4;
always @(a or b)
begin
if(a>b)
q1=1;
else
q1=0;
if(a<b)
q2=1;
else
q2=0;
if(a==b)
q3=1;
else
q3=0;
end
endmodule
TRUTH TABLE

SIMULATION RESULT

Generic Skills / Outcomes:

 Simplify Boolean expressions using algebraic method
 Design karnaugh maps and use them to simplify Boolean expressions
Result:
EXPERIMENT N0:3. Write HDL code to describe the functions of a full Adder Using three modeling
styles

Objectives:
 To write the code to describe the functions of a Full Adder using three modeling styles.

 To execute the code to describe the functions of a Full Adder using three modeling styles.

RTL Schematic

Truth Table
DATA FLOW

VHDL CODE VERILOG CODE

library IEEE; module fulladder ( a, b, cin,sum,cout);
use IEEE.STD_LOGIC_1164.ALL; input a, b,cin;
use IEEE.STD_LOGIC_ARITH.ALL; output sum, cout;
use IEEE.STD_LOGIC_UNSIGNED.ALL; assign sum= a ^ b ^ cin;
assign cout= (a & b) | (b & cin) | (cin & a);
entity fulladder is endmodule
Port ( a,b,cin : in std_logic;
sum,cout : out std_logic);
end fulladder;

architecture data of fulladder is

Begin
sum<=a xor b xor cin;
cout<= ( a and b) or ( b and cin) or ( cin and a);
end data;

BEHAVIORAL STYLE

VHDLCODE VERILOG CODE

library IEEE; module fulladd(a,b,cin,sum,cout);
use IEEE.STD_LOGIC_1164.ALL; input a,b,cin;
use IEEE.STD_LOGIC_ARITH.ALL; output sum,cout;
use IEEE.STD_LOGIC_UNSIGNED.ALL; reg sum,cout;
always@(a,b,cin)
entity fulladder_beh is Begin
Port ( a,b,cin : in std_logic; sum,cout : out std_logic); sum= a ^ b ^ cin;
end fulladder_beh; cout= (a & b) | (b & cin) | (cin & a);
end
architecture Behavioral of fulladder_beh is endmodule
Begin
process( a,b,cin)
Begin
sum<=a xor b xor cin;
cout<=(a and b)or(a and cin)or(b and cin);
end process;
end Behavioral;
End
 STRUCTURAL MODELLING
VHDLCODE VERILOG CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; //HALF ADDER
use IEEE.STD_LOGIC_ARITH.ALL; module fa(a,b,cin,y,cout);
use IEEE.STD_LOGIC_UNSIGNED.ALL; input a,b,cin;
entity fa_1 is output y,cout;
port(a,b,cin:in std_logic; wire s1,a1,a2,a3,a4;
s,cout:out std_logic); xor xor1(s1,a,b);
end fa_1; xor xor12(y,cin,s1);
architecture fa of fa_1 is and and1(a1,a,b);
component xor_2 and and12(a2,b,cin);
port(a,b:in std_logic; and and13(a3,a,cin);
c:out std_logic); or or1(a4,a1,a2);
end component; or or12(cout,a4,a3);
endmodule
component and_2
port(a,b:in std_logic;
c:out std_logic);
end component;

component or_2
port(a,b:in std_logic;
c:out std_logic);
end component;

signal s1,a1,a2,a3,a4:std_logic;
begin
x1:xor_2 port map(a,b,s1);
x2:xor_2 port map(cin,s1,c);
z1:and_2 port map(a,b,a1);
z2:and_2 port map(b,cin,a2);
z3:and_2 port map(a,cin,a3);
u1:or_2 port map(a1,a2,a4);
u2:or_2 port map(a4,a3,cout);
end fa;

SIMUALTION RESULT
 Generic Skills / Outcomes:
 Implementing Boolean expressions using half adder and OR gate
 Describe logic circuits using HDL control structures IF/ELSE, IF/ELSIF, and CASE.

Result:
EXPERIMENT No:4. Write a model for 32 bit ALU using the schematic diagram shown below
 ALU should use combinational logic to calculate an output based on the Four bit op-code
input.
 ALU should pass the result to the out bus when enable line in high, and Tri-state the out
bus when the enable line is low.
 ALU should decode the 4 bit op-code according to the given in example below.

Objectives:
 Study the ALU given in the question and to write the code for the same.
 To execute the ALU given in the question and to Synthesize the code for the
same.

RTL Schematic

Opcode Y
0001 ADD
0010 SUB
0011 COMPLEMENT
OF A
0101 AND
0110 OR
0111 NAND
1000 EXOR
OTHERS X

VERILOG

module ALU_MIXED(a,b,opcode,enable,y);
input [3:0] a,b;
input [3:0] opcode;
input enable;
output [7:0] y;
reg [7:0] y;
always@(a,b,enable,opcode)
begin
if(enable==1'b1)
begin
case (opcode)
4'b0001 : y = a + b;
4'b0010 : y = a - b;
4'b0011 : y = ~ a;
4'b0101 : y = a & b;
4'b0110 : y = a | b;
4'b0111 : y = ~(a & b);
4'b1000 : y = a ^ b;
default: y=8'd0;
endcase
end
else
begin
y=8'd0;
end
end
endmodule

Generic Skills / Outcomes:

 An arithmetic logic unit (ALU) is a digital circuit which performs arithmetic, logic and shift
operations on two n-bit digital words.
 Functionally, an ALU can be divided up into three circuits: the arithmetic circuit, the logic
circuit and the shift circuit. Using HDL all operations are verified.
EXPERIMENT No:5 Write verilog code for the following flip-flops, SR, D, JK & T.

5a. SR FLIP FLOP

Objectives:
 Design the following flip-flops, SR, D, JK, T.
 Execute to the design and synthesize it.

Truth Table
CLK s r Q Qb
0 x x Q Qb
1 0 1 0 1
1 1 0 1 0
1 1 1 Not defined
1 0 0 Q Qb

RTL Schematic
VERILOG CODE
module sr(sr,clk,q,qb);
input clk;
input[1:0]sr;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
case(sr)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=1'bZ;
endcase
qb=~q;
end
endmodule

Simulation Waveforms:
5b. JK FLIP FLOP
Logic Symbol RTL Schematic

TruthTable
CLK J K Q Qb
0 x x Q Qb
1 0 1 0 1
1 1 0 1 0
1 1 1 Qb Q
1 0 0 Q Qb
VERILOG CODE FOR TEST
BENCH WAVEFORM
VERILOG CODE FOR
DOWNLOADING ONTO A module jkff1(jk,clk,q,qb);
FPGA input clk;
module jkff1(jk,clk,q,qb); output q,qb;
input clk; reg q=0,qb=1;
output q,qb; input [1:0]jk;
reg q=0,qb=1;
input [1:0]jk; always@(posedge clk)
begin
reg[24:0] clkd; case (jk)
2'b00:q=q;
always@(posedge clk) 2'b01:q=0;
Begin 2'b10:q=1;
clkd = clkd+1; 2'b11:q=~q;
End endcase
qb=~q;
always@(posedge clkd[21]) end
Begin endmodule
case (jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
Endcase
qb=~q;
End endmodule
Simulation waveforms:

Result:

5c. D FLIP FLOP

RTL Schematic
Truth Table

CLK D Q Qb OPERATION
0 x Q Qb No change
1 0 0 1 Reset
1 1 1 0 Set

VERILOG CODE
module dff(d,clk,q,qb);
input d,clk;
output q,qb;
reg q=0,qb=1;
always@(posedge clk)
begin
q= d;

end
qb=~q;
endmodule
LOGIC Symbol

SIMULATION RESULT

Result:
5d. T FLIP FLOP

RTL Schematic

Logic Symbol
Truth Table

CLK T Q Qb OPERATION
0 x Q Qb No Change
1 0 Q Qb No Change
1 1 Qb Q Toggle

VERILOG CODE FOR VERILOG CODE FOR

TEST BENCH DOWNLOADING ONTO A
module tff(t,clk,q,qb);
WAVEFORM FPGA
input t,clk; module tff(t,clk,q,qb);
output q,qb; input t,clk;
reg q=0,qb=1; output q,qb;
always@(posedge clk)
reg q=0,qb=1;
Begin
if(t==1) reg [24:0] clkd;

q=~q; always@(posedge clk)

Else Begin
q=q; clkd = clkd+1;
end End
qb=~q;
End
Endmodule always@(posedge clkd[21])
Begin
if(t==1)
q=~q;
Else
q=q;
qb=~q; end endmodule
Simulation Waveform:

Result:

Generic Skills / Outcomes:

 Describe the action of a rising-edge-triggered flip-flop.
 Draw a timing diagram for a flip-flop.
EXPERIMENT-6

6.1) SYNCHRONOUS RESET COUNTER

RTLSchematic TruthTable

Clock Reset Current Next

State State
1 1 xxx 0000
1 0 0000 0001
1 0 0001 0010
1 0 0010 0011
1 0 0011 0100
1 0 0100 0101
1 0 0101 0110
1 0 0110 0111
1 0 0111 1000
1 0 1000 1001
1 0 1001 1010
1 0 1010 1011
1 0 1011 1100
1 0 1100 1101
1 0 1101 1110
1 0 1110 1111

0 x 1111 0000
VERILOG CODE
module syncnt(clk,reset,count);
input clk,reset;
output [3:0] count;
reg[3:0]count=4'b0000;
reg[24:0] clkd;

always@(posedge clk)
Begin
clkd = clkd+1;
End

always @(posedge clkd[20])

Begin
if(reset==1)
count = 4'b0000;
Else
count = count+1;
End
Endmodule
HDL Lab (15ECL58)Manual Vsem

PART- B
INTERFACING
PROGRAMS

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EXPERIMENT No:1

1(a). Write a HDL code to control speed, direction of D.C motor

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity DCMOTORSP3 is
port(start,dir,clk:in std_logic;
pwm_out:out std_logic;
out_dc:out std_logic_vector(1 downto 0) );
end DCMOTORSP3;

architecture dcmotor_a of DCMOTORSP3 is

signal clk1: std_logic;
signal div: std_logic_vector(24 downto 0);
begin
process(clk,start)
begin
if(start='0') then
div<="0000000000000000000000000";
elsif(clk'event and clk='1')then
div<= div+1;
end if ;
clk1<=div(14);
end process;
process(clk1)
begin
if(clk1'event and clk1='1')then
if start='0' then
out_dc<="00";
elsif start='1' and dir='1' then
out_dc<="10";
pwm_out<='1';
elsif start='1' and dir='0' then
out_dc<="01";
pwm_out<='1';
end if;
end if;
end process;
end dcmotor_a;

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1(b).Write a HDL code to control speed, direction of stepper motor

Library IEEE; -- library declaration

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity STEPPERSP3 is -- entity declaration

Port (clk: in STD_LOGIC;
rst: in STD_LOGIC; --start, stop:in std_logic;
dir: in std_logic; -- dir1, dir2: in std_logic;
out_stm: out STD_LOGIC_vector (3 downto 0));
end STEPPERSP3;

architecture stm_st_a of STEPPERSP3 is -- architecture declaration

type state_type is (s0,s1,s2,s3);
signal state: state_type; -- signal assignment
signal div: std_logic_vector (20 downto 0);
signal lk, clkwise, start: std_logic;

begin
process (clk, rst)
begin
if (rst='1') then
div<= (others=>'0');
elsif (clk'event and clk = '1') then
div <= div + 1;
end if;
end process;
lk <=div(19);

process (lk, dir) -- direction control

begin
if lk='1' and lk'event then
if dir='1' then
clkwise<=not clkwise;
end if;
end if;
end process;
process (lk, rst, clkwise)
begin
if (rst='1') then
state <=s0;
elsif lk'event and lk='1' then
if clkwise='0' then
case state is

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when s0=> state<=s1;

when s1=> state<=s2;
when s2=> state<=s3;
when s3=> state<=s0;
when others=>null;
end case;
elsif clkwise='1' then
case state is
when s3=> state<=s2;
when s2=> state<=s1;
when s1=> state<=s0;
when s0=> state<=s3;
when others=>null;
end case;
end if;
end if;
end process;

with state select

out_stm<= "0110" when s0,
"1010" when s1,
"1001" when s2,
"0101" when s3;
end stm_st_a;

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EXPERIMENT No:2. Write HDL code to generate different waveforms (square, triangle,ramp
etc.,) using DAC

2 a).SQUARE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DACSQR is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end DACSQR;

architecture Behavioral of DACSQR is

signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 7);
signal en:STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif
rising_edge(temp(3)) then
if cnt<255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif
cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;

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2 b).TRIANGULAR WAVE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DACTRI is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end DACTRI;

architecture Behavioral of DACTRI is

signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 8);
signal en:STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="000000000";
elsif
rising_edge(temp(3)) then
cnt<=cnt+'1';
if cnt(0)='1' then
dac<=cnt(1 to 8);
else

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dac<=not(cnt(1 to 8));
end if;
end if;
end process;
end Behavioral;

2c).RAMP Wave

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SAWTOOTH is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
dac : out STD_LOGIC_VECTOR (7 downto 0));
end SAWTOOTH;

architecture Behavioral of SAWTOOTH is

signal temp:STD_LOGIC_VECTOR (3 downto 0);
signal cnt:STD_LOGIC_VECTOR (0 to 8);

begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="000000000";
elsif

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rising_edge(temp(3)) then
cnt<=cnt+'1';

end if;
end process;
dac<=cnt(1 to 8);
end Behavioral;

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EXPERIMENT No:3 Write a HDL code for displaying hex keypad data on seven segment
display

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity GKBDSP3 is
Port (clk: in std_logic;
rst: in std_logic;
row: out std_logic_vector (3 downto 0);
col: in std_logic_vector ( 3 downto 0);
En1,En2,En3,En4,En5,En6 : out std_logic;
seg_dis: out std_logic_vector (6 downto 0));
end GKBDSP3;

architecture behave of GKBDSP3 is

type state is (s0, s1, s2, s3);
signal st:state:= s0;
signal clkdiv: std_logic;
signal col1, col2: std_logic_vector (3 downto 0);
signal clk_div: std_logic_vector (15 downto 0);
begin
En1 <= '0'; En2 <= '0'; En3 <= '0';
En4 <= '0'; En5 <= '0'; En6 <= '0';

clkdiv <= clk_div (15);

process (clk, rst)
begin
if rst<='0'then
if clk'event and clk = '1' then
clk_div <= clk_div + '1';
else
null;
end if;
end if;
end process;

process (clkdiv)
begin
if clkdiv'event and clkdiv = '1' then
col1 <= col;
col2 <= col1;

case st is

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when s0 => row <= "1110";

case col2 is
when "1110" => seg_dis <= "0111111";
when "1101" => seg_dis <= "0000110";
when "1011" =>seg_dis <= "1011011";
when "0111"=> seg_dis <= "1001111";
when "1111" => st <= s1;
when others => null;
end case;

when s1 => row <= "1101";

case col2 is
when "1110" =>seg_dis <= "1100110";
when "1101" =>seg_dis <= "1101101";
when "1011" => seg_dis <= "1111101";
when "0111"=> seg_dis <= "0000111";
when "1111" => st <= s2;
when others => null;
end case;

when s2 =>row <= "1011";

case col2 is
when "1110" => seg_dis <= "1111111";
when "1101" =>seg_dis <= "1101111";
when "1011" => seg_dis <= "1110111";
when "0111"=> seg_dis <= "1111100";
when "1111" =>st <= s3;
when others =>null;
end case;

when s3 =>row <= "0111";

case col2 is
when "1110" =>seg_dis <= "0111001";
when "1101" => seg_dis <= "1011110";
when "1011" => seg_dis <= "1111001";
when "0111"=>seg_dis <= "1110001";
when "1111" => st <= s0;
when others => null;
end case;
end case;
end if;
end process;
end behave;

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Truth Table:

Display a b c d e f g

0 1 1 1 1 1 1 0
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 1 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1

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Viva Questions

1. What are inertial and transport delays ?

2. What does `timescale 1 ns/ 1 ps’ signify in a verilog code?
3. How to generate sine wav using verilog coding style?
4. How do you implement the bi-directional ports in Verilog HDL?
5. How to write FSM is verilog?
6. What is verilog case (1)?
7. What are Different types of Verilog simulators available?
8. How can you model a SRAM at RTL Level?
9. How does look-a head carry adder speed up the addition process.
10. What is parity bit generator.
11. What are applications of flip flops.
12. What is shift register. Write the VHDL code of Shift register.
13. Give logic diagram of 4-bit buffer register.
14. What are different types of ROM’s.
15. What is the disadvantage of serial adder. For which applications are they preffered.
16. What is difference between counting sequence of an up-counter and down-counter.
17. What are hardware description languages
18. What are applications of multiplexers
19. What do you mean by latch and gated latch
20. How does PLA differ from ROM.
21. How do you convert S_R flip flop to J-K flip flop.
22. What is key difference between sequential and combinational circuits
23. Discuss the Difference between array and records types.
24. What is meant by operator overloading? Give an example.
25. what is the difference between function and procedure in VHDL? Give suitable examples.
26. Write down the truth table and VHDL code for the 4-bit left to right shift register. Also draw
the circuit and output waveforms
27. What is the difference between variable and signal.
28. Differentiate between a process and wait statement.

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