Introduction to HDL

Day -3

STC on HDL for Digital System Design 1

 What is HDL
hardware description language or HDL is any language from a class of
computer languages for formal description of electronic circuits. It can
describe the circuit's operation, its design and organization, and tests to
verify its operation by means of simulation.

A Hardware Description Language (HDL) is a standard text-based expression

of the temporal behaviour and/or (spatial) circuit structure of an electronic
system. In contrast to a software programming language, an HDL's syntax
and semantics include explicit notations for expressing time and
concurrency which are the primary attributes of hardware. Languages
whose only characteristic is to express circuit connectivity between a
hierarchy of blocks are properly classified as netlist languages

STC on HDL for Digital System Design 2

 Different Types of HDL
The two most widely-used and well-supported HDL varieties used in industry are:
• VHDL Verilog
Others include:
• Advanced Boolean Expression Language (ABEL)
• AHDL (Altera HDL, a proprietary language from Altera)
• Atom (behavioral synthesis and high-level HDL based on Haskell)
• Confluence (a functional HDL; has been discontinued)
• CUPL (a proprietary language from Logical Devices, Inc.)
• HDCaml (based on Objective Caml)
• Hardware Join Java (based on Join Java)
• HML (based on SML)
• Hydra (based on Haskell)
• JHDL (based on Java)
• Lava (based on Haskell)
• Lola (a simple language used for teaching)
• MyHDL (based on Python)
• PALASM (for Programmable Array Logic (PAL) devices)
• Ruby (hardware description language)
• RHDL (based on the Ruby programming language)
• CoWareC, a C-based HDL by CoWare. Now discontinued in favor of SystemC
• SystemVerilog, a superset of Verilog, with enhancements to address system-level design and verification
• SystemC, a standardized class of C++ libraries for high-level behavioral and transaction modeling of digital hardware at a high level of abstraction, i.e.
system-level
• Analog circuit design
• Verilog-AMS
• VHDL-AMS

STC on HDL for Digital System Design 3

 What is VHDL
VHDL (VHSIC hardware description language) is commonly used as a design-
entry language for field-programmable gate arrays and application-specific
integrated circuits in electronic design automation of digital circuits.

VHDL was originally developed at the behest of the US Department of Defense in

order to document the behavior of the ASICs that supplier companies were
including in equipment. That is to say, VHDL was developed as an alternative
to huge, complex manuals which were subject to implementation-specific
details.

The initial version of VHDL, designed to IEEE standard 1076-1987

The second issue of IEEE 1076, in 1993
In June 2006, VHDL Technical Committee of Accellera (delegated by IEEE to
work on next update of the standard) approved so called Draft 3.0 of VHDL-
2006

STC on HDL for Digital System Design 4

VDHL Tools

STC on HDL for Digital System Design 5

 Simulation
• an imitation of some real thing, state of affairs, or process.
• The act of simulating something generally entails representing certain key
• characteristics or behaviours of a selected physical or abstract system

• Physical simulation refers to simulation in which physical objects are substituted

for the real thing. These physical objects are often chosen because they are smaller or
cheaper than the actual object or system.

• Interactive simulation is a special kind of physical simulation, often referred to as

a human in the loop simulation, in which physical simulations include human operators,
such as in a flight simulator or a driving simulator.

• Computer simulation is an attempt to model a real-life or hypothetical situation

on a computer so that it can be studied to see how the system works. By changing
variables, predictions may be made about the behaviour of the system.

STC on HDL for Digital System Design 6

 Simulation Tool

Simulation is essential
1) model is very complex with many variables and interacting components;
2) underlying variables relationships are nonlinear;
3) model contains random variates;
4) model output is to be visual as in a 3D computer animation

STC on HDL for Digital System Design 7

Simulation Tool For VHDL

STC on HDL for Digital System Design 8