Real World Problems

Synthesize-able Designs
Day –10,11

STC on HDL for Digital System Design 1

Full of Parameters
Wants
Understanding What is required
•Input
•Keyboard, switch, ADC etc.
•Output
•Led, LCD , Buzzer, Motors, etc
•Control
•Control Logic(FPGA)
• Smartness

STC on HDL for Digital System Design 2

 Interfacing Key/Keyboard

•Keyboard are organized in a matrix of rows & column

•Controller access both rows & columns via I/o ports
•When a key is pressed a row & column make a contact

STC on HDL for Digital System Design 3

Connection (Rows-Column)
•Rows are connected to o/p
•Column are connected to I/p
•No key is pressed, reading I/p port will give 1’s for all
column,as they are connected to Vcc
•Rows grounded – key is pressed only one column is 0.

STC on HDL for Digital System Design 4

 Sample Program
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;

process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;

STC on HDL for Digital System Design 5

Interfacing Led/LCD

STC on HDL for Digital System Design 6

Character Set LCD Command
Code (Hex) Command to LCD Instruction Register
1 Clear Display
2 Return Home
4 decrement cursor(shift cursor to left)
6 increment cursor(shift cursor to right)
5 shift display right
7 shift display left
8 display off, cursor off
A display off, cursor on
C display on cursor off
E dislay on, cursor blinking
F shift cursor posttion to left
10 shift cursor posttion to right
14 shift cursor posttion to left
18 shift entire display to left
1C shift entire display to rightt
80 force cursor brgining to 1st line
C0 force cursor brgining to 2nd line
38 2 lines & 5x7 matrix

STC on HDL for Digital System Design 7

display
Sample Program
process(sdspclk)
variable vdspseq : integer range 0 to 15; variable vdspnum : integer range 0 to 15; variable i1 : integer;

type tlcdtyp is array(0 to 15) of std_logic_vector (7 downto 0);

constant tlcddat : tlcdtyp = ("00111000", "00001110", "00000010", "00000001", "01000001", "01000100", "01001101", "00100000",
"01000001", "01000100", "01001101", "00100000","01000001","01000100","01001101","00100000" );

begin
if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if
if(vdspseq < 4) then
plcddat <= tlcddat(vdspseq);
vdspnum := 0;
else
plcddat <= tlcddat(vdspseq);
tchr1 <= mystr(vdspnum);
plcddat <= std_logic_vector(to_unsigned(character'pos(tchr1),8));
end if;
plcdrw <= '0';
if(vdspseq < 4) then
plcdrs <= '0';
else
plcdrs <= '1';
end if;
end process; STC on HDL for Digital System Design 8
Interfacing Seven Segment Display

STC on HDL for Digital System Design 9

Interfacing Multiplexed Seven Segment Display

STC on HDL for Digital System Design 10

 Sample Program
process muxdisp
process(sdspmux)
type tseg7 is array(0 to 15) of std_logic_vector (6
downto 0);
constant segval : tseg7 :=
("0000000","0000000","0000000","0000000",
"1110001","1110011","1111101","1110111",
"1011011","1101101","1011100","1011100",--
"0111001","1110011","0111000","1011110",--
"1101111","1101101","0000111","1011011",
"0000000","0000000","0000000","0000000");

begin
if(sdspmux = "1110") then pdspseg <= segval(sdspnum);
elsif(sdspmux = "1101") then pdspseg <= segval(sdspnum+1);
elsif(sdspmux = "1011") then pdspseg <= segval(sdspnum+2);
elsif(sdspmux = "0111") then pdspseg <= segval(sdspnum+3);
else pdspseg <= "0000000";
end if;
end process;

STC on HDL for Digital System Design 11

Interfacing Stepper Motor

STC on HDL for Digital System Design 12

 Sample Program

process(sstpcnt)
begin
if (sstpcnt = "00") then pstpsig <= "0001";
elsif(sstpcnt = "01") then pstpsig <= "0111";
elsif(sstpcnt = "10") then pstpsig <= "1110";
elsif(sstpcnt = "11") then pstpsig <= "1000";
end if;
end process;

STC on HDL for Digital System Design 13

Integrating The Elevator Controller

STC on HDL for Digital System Design 14

 End

STC on HDL for Digital System Design 15