Chapter 3: Software Description

Xilinx Vivado
OVERVIEW

Vivado™ supports design entry in traditional HDL like VHDL and

Verilog. It also supports a graphical user interface-based tool called
the IP Integrator (IPI) that allows for a Plug-and-Play IP Integration
Design Environment. The Vivado ML Edition delivers the best-in-class
synthesis and implementation for today’s complex FPGAs and SOCs
with built-in capabilities for timing closure and methodology. The
UltraFast methodology report (report_methodology) that is available
in the default flow of Vivado, helps users constrain their design,
analyze results, and close timing.

The Xilinx Vivado Design Suite can be described as a

software suite manufactured by Xilinx. This is majorly for the analysis
and synthesis of HDL (hardware description language) designs.
Furthermore, this supersedes the Xilinx ISE, because it comes with
extra features for high-level synthesis and system on chip
development. Also, Vivado has to do with ground-up rethinking and
rewriting of the whole design flow (in contrast to the ISE). Similar to
ISE’s later versions, the Xilinx Vivado features an in-built logic
simulator. In addition, Xilinx Vivado introduces high-level synthesis,
using a toolchain, which helps in converting C code to the
programmable logic. Bringing in the Xilinx Vivado design suite to
replace the already existing Xilinx ISE (15 years old) took a thousand
 ABOUT XILINX VIVADO
Design Optimization (ML-Based)

 Breakthrough ML algorithms which helps in accelerating the

design closure
 Also, there’s 10% average and a QoR gain of about 50%

Accelerate the Design Closure

 This newly developed Vivado® ML Edition offers breakthrough

quality improvements that can reach 50% (and an average of
10%) on any complex design, in contrast to the Vivado HLx
Edition.

 There are new algorithms and features, which include logic

optimization (ML-based), delay estimation, congestion
estimation, as well as intelligent runs of design, and automated
strategies which help in reducing the iterations of the timing
closure.

A Design Environment that is Collaborative

 First-ever graphical IP flow of the industry featuring a modular

design
 Has productivity boost featuring a team-based design

Increase in Productivity

 Better collaborative design featuring the Vivado IP Integrator

that allows modular design making use of the new features.
 Helps in promoting a design methodology (team-based). It also
allows a strategy that helps in handling large designs including
multisite collaboration.
New DFX Features (Advanced)

 It allows the efficient and good use of those resources having

reconfigurable properties
 On average, there is a 5x reduction in compile time reduction

Reduction in Compile Time

 The Abstract Shell concept is introduced by Xilinx. This allows the

user to define many modules in the system in order to be
incrementally compiled, as well as in parallel.
 The feature enables an average reduction in compile time of 5x.
The reduction can also reach 17x in contrast to the full-system
traditional compilation.
 Also, the Abstract Shell assists in protecting the IP of the
customer. It achieves this by concealing the details of the design
when outside the module

FEATURES OF THE XILINX VIVADO

Vivado Design Flow:

Design Entry & Implementation
Ip integrator:

 The Vivado™ ML Edi on sha ers the RTL design produc vity plateau by
providing the industry’s first plug-and-play IP integra on design
environment, with its IP Integrator feature.
 Vivado IP Integrator provides a graphical and Tcl-based, correct-by-
construc on design development flow. It provides a device and pla orm
aware, interac ve environment that supports intelligent auto-connec on
of key IP interfaces, one-click IP subsystem genera on, real- me DRCs,
and interface change propaga on, combined with a powerful debug
capability.
 Designers work at the “interface” and not “signal” level of abstrac on
when making connec ons between IP, greatly increasing produc vity.
O en mes this is using industry standard AXI4 interfaces, but dozens of
other interfaces are also supported by IP integrator.
 Working at the interface level, design teams can rapidly assemble complex
systems that leverages IP created with Vi s HLS, Model Composer, AMD
SmartCore™ and LogiCORE™ IP, Alliance Member IP as well as your own
IP. By leveraging the combina on of Vivado IPI and HLS customers are
saving up to 15X in development costs versus an RTL approach.
Logic Synthesis

 Vivado logic synthesis is a design crea on tool enabling hardware

designers to produce op mal pla orms, IP, and custom designs
targe ng all the latest AMD devices. Logic synthesis translates
Register Transfer Level (RTL) designs wri en in SystemVerilog,
VHDL, and Verilog into a synthesized netlist of library cells for
downstream Implementa on. Being aware of the target
technology, synthesis can infer func ons from RTL descrip ons
that map directly to dedicated silicon structures including
LUTRAMs, Block RAMs, shi registers, adder-subtractors, and
DSP blocks. Synthesis results are driven using a ributes, tool
op ons, and Xilinx Design Constraints (XDC) to meet design
goals. Logic synthesis works within Vivado Projects and Tcl
scrip ng and provides a solid founda on for other high-level
design methods that generate RTL descrip ons including High-
Level Synthesis and IP integrator.
 Logic synthesis has introduced Machine Learning to help speed
up compila on. ML models improve overall efficiency by
predic ng the synthesis op miza ons needed for different
parts of the design.
 Design Methodology:

 When used with Vivado, the UltraFast methodology helps define

proper constraints, helps to properly drive the tools and analyze
results, and improves overall produc vity. The UltraFast Design
Methodology is a collec on of best hardware design prac ces
accumulated from many years of experience of Vivado experts
and their design closure successes on customer designs that
push the limits of the tools and technology.
Implementa on:

 Vivado implementa on is used for placing and rou ng AMD

device designs. It supports various design sizes, from small to
 large devices. U lizes advanced algorithms for par oning,
placement, and rou ng. Machine learning guides the process,
improving results in less me. Xilinx Design Constraints ensure
design goals are met. Offers different. opera on modes for
simplicity or customiza on. Detailed analysis of ming,
u liza on, and power metrics is available. Design database can
be saved and restored for flexibility.
Verification and Debug

Simula on flow

 Vivado enables behavioral, post-synthesis and post-implementa on

(func onal or ming) si
 mula ons for the fully integrated Vivado Simulator and 3rd party
HDL simulators. The Vivado IDE supports all major simulators in
integrated mode for interac ve simula on users and script mode for
advanced verifica on engineers.

Programming and Debug

 Vivado Debug offers a variety of solu ons to help users debug their
designs easily, quickly, and more effec vely. These solu ons consist
of tools, IPs, and flows that enable a wide range of capabili es from
logic to system level debug while the user design is running in hard
ADVANTAGES
 Meeting Fmax targets:
  Achieving your fMAX target in a high-speed design is one of the
most challenging phases of the hardware design cycle. Vivado
brings unique features such as Report QoR Assessment
(RQA), Report QoR Sugges ons (RQS) and Intelligent Design Runs
(IDR) –these features help you close ming. Using RQA, RQS and
IDR will help converge on your performance goals in days instead
of weeks resul ng in huge produc vity gains.

 Enable Faster Design Iterations

 Design iterations are common as devlopers add new

features and debug their design. In many cases these
iterations are incremental changes and in most cases the
changes are within a small portion of the design. The
Vivado ML Edition offers two key technologies that
significantly reduce design iteration times: Incremental
compile and Abstract Shell.
 Accurate power Estimation

 Power es ma on is cri cal for many decisions during the

adap ve SoC and FPGA design process—from device selec on to
system-level power budge ng and thermal design. For many
years, Xilinx Power Es mator (XPE) has been a leading FPGA
power es ma on tool. As adap ve SoCs and FPGAs increase in
size and complexity, power es ma on capabili es must scale
accordingly, especially as designs include increasing numbers of
new, complex, hard IP blocks

RESOURCES

Self-Service Resources for Vivado

Documentation Portal
Robust online search and navigation of HTML-based technical content.
 Design Hubs

Current technical content for specific design tasks, devices, and t

Training

Access our library of training materials across a variety of subjects.

Support Community

Expert Support, Design Advisories, Known Issues & Community.