Seminar On HDL's and HVL's

Evolution of HDL’s,
HVL’s and Concepts of

Verification
By K.HARISH
10-10-2023 CONFIDENTIAL AND DO NOT COPY 1

Agenda
Evolution of Integrated Circuits
Evolution of Computer Aided Digital Design
Emergence of Hardware Description Languages (HDLs)
Limitations of HDLs
Emergence of Hardware Verification Languages (HVLs)
Key Features of Hardware Verification Languages (HVLs)
Verification Concepts
10-10-2023
CONFIDENTIAL AND DO NOT COPY 2
Introduction
 Digital circuit design has evolved rapidly over the past.
 Digital systems are precise, less noisy than analog systems.
 Digital data can be easily stored and processed.
 They are built using basic blocks called transistors.
10-10-2023
The First Transistor
Location: Bell Labs

Scientists: John Bardeen, Walter Brattain, and William Shockley
Material: Germanium
Impact: Revolutionized electronics, replacing vacuum tubes
Recognition: Nobel Prize in Physics (1956)
Legacy: Paved the way for the modern semiconductor industry

Evolution of Integrated Circuits
 Scaling transistors down packed more into the same space, enabling
greater functionality.
 This evolution led to the invention of Integrated Circuits (ICs).
 ICs revolutionized electronics, integrating multiple components on
one chip.
10-10-2023
Evolution of Computer Aided Digital Design
 In the beginning, designs had only a few gates, and thus it was
possible to verify these circuits on paper or with breadboards.
10-10-2023
Evolution of Computer Aided Digital Design
As designs grew larger and more complex, verification using paper
or breadboards became impossible.
Computer-aided techniques became critical for verification and
design of VLSI digital circuits.
Logic simulators came into existence to verify the functionality of
these circuits before they were fabricated on Chip.

Emergence of HDLs
 Designers felt the need for a standard language to describe digital
circuits.
 Thus, Hardware Description Languages (HDLs) came into existence.

Hardware Description Language
Designers began to use gate-
level models described in a HDLs
help with verification before
fabrication.
10-10-2023
Hardware Description Languages
 When the number of gates in the
designs are in the ranges of 100,000
gate designs, these gate-level models
also became complex for the functional
specification.
 Designers again turned to HDLs for
help – abstract behavioral models
written in an HDL provided both a
precise specification and a framework
for design exploration.
10-10-2023
 Even though HDLs were popular for logic verification, designers
had to manually translate the HDL-based design into a schematic
circuit with interconnections between gates.
 Digital circuits could be described at a register transfer level (RTL)
by use of an HDL.
 The designer had to specify how the data flows between registers
and how the design processes the data.
 The details of gates and their interconnections to implement the
circuit were automatically extracted by logic synthesis tools from the
RTL description.
10-10-2023
 HDLs also began to be used for system-level design.
 HDLs were used for simulation of system boards, interconnect
buses, FPGAs (Field Programmable Gate Arrays), and PALs
(Programmable Array Logic).
Comprehensive and easy to learn
 Most popular logic synthesis tools support verilog HDL
 All fabrication vendors provide Verilog HDL libraries.
10-10-2023
Verilog HDL
Invented by Philip Moorby in 1983/84.
The original standard was IEEE 1364
The first version was published in 1995.
Revised in 2001 and 2005.
Allows different levels of abstraction to be mixed in the same
design.
Single language for design and testbench.
10-10-2023
Limitations of HDLs in Terms of Verification
 Complexity Handling: HDLs can struggle to handle the complexity
of modern hardware designs. As designs become larger and more
intricate, it becomes increasingly challenging to write exhaustive
testbenches and verify all possible scenarios.
 Limited Abstraction for Verification: While HDLs provide

abstraction for design, they may not offer the same level of
abstraction for verification. Writing comprehensive testbenches and
assertions in HDLs can be labor-intensive and error-prone, making it
difficult to thoroughly verify a design.

Emergence of Hardware Verification Language
 As designs grew complex, verification also became complex.
 Commercial solutions like “OpenVera” from Synopsys and “e” from
Cadence introduced.
 Later System Verilog was introduced by the Accellera.
In 2005, System Verilog has become an IEEE P1800 standard.

Typical features of HVL’s
 Constrained Random Stimulus Generation
 OOPs concepts
 Support assertions
 Functional Coverage and Code Coverage
 Better memory management
10-10-2023
Constrained Randomization
70 % of design effort goes into verification.
Quick and Improved bug detection is achieved using constrained
randomization.

Object Oriented Programming in SV
Object Oriented Programming in SystemVerilog is supported through
the class data type
 OOP enables the following concepts
• Encapsulation
• Inheritance
• Data hiding
• Polymorphism
 Classes can be used to model the reusable verification
environments.

System Verilog Testbench

Code Coverage
Code coverage is a metric that indicates how much of the code of
the DUT has been exercised by the test bench.
It includes line, branch, toggle, expression, FSM coverage.
Automated and supported by all major simulators.
100% code coverage is not sufficient for verification closure.

Functional Coverage
A user defined metric that measures how much of the design
specification has been exercised in verification.
It is manually written by the verification engineers.
Cover points and cover bins are defined to capture the coverage.

Conclusion
In summary, the evolution of digital circuit design, from
transistors to modern integrated circuits, has been shaped by the
adoption of Hardware Description Languages (HDLs) and Hardware
Verification Languages (HVLs). These tools have revolutionized our
ability to design and verify complex digital systems. As we continue to
push the boundaries of technology, innovation remains at the
forefront, driving progress in this dynamic field.

Thank You

Back Up

Q&A

Seminar On HDL's and HVL's

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Seminar On HDL's and HVL's

Uploaded by

Copyright:

Available Formats

Evolution of HDL’s,

HVL’s and Concepts of

10-10-2023 CONFIDENTIAL AND DO NOT COPY 1

Location: Bell Labs

10-10-2023 CONFIDENTIAL AND DO NOT COPY 4

10-10-2023 CONFIDENTIAL AND DO NOT COPY 7

10-10-2023 CONFIDENTIAL AND DO NOT COPY 8

 Limited Abstraction for Verification: While HDLs provide

10-10-2023 CONFIDENTIAL AND DO NOT COPY 14

10-10-2023 CONFIDENTIAL AND DO NOT COPY 15

20-07-2023 CONFIDENTIAL AND DO NOT COPY 17

20-07-2023 CONFIDENTIAL AND DO NOT COPY 18

20-07-2023 CONFIDENTIAL AND DO NOT COPY 19

It includes line, branch, toggle, expression, FSM coverage.

Automated and supported by all major simulators.

100% code coverage is not sufficient for verification closure.

20-07-2023 CONFIDENTIAL AND DO NOT COPY 20

20-07-2023 CONFIDENTIAL AND DO NOT COPY 21

20-07-2023 CONFIDENTIAL AND DO NOT COPY 22

20-07-2023 CONFIDENTIAL AND DO NOT COPY 23

20-07-2023 CONFIDENTIAL AND DO NOT COPY 24

20-07-2023 CONFIDENTIAL AND DO NOT COPY 25

You might also like