CHAPTER 1

VERY LARGE SCALE INTEGRATION (VLSI)

INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating and integrated

circuits (IC) by combining hundreds of thousands of transistors or devices into a single chip.
VLSI began in the 1970s when complex semiconductor and communication technologies
were being developed. The microprocessor is a VLSI device. Before the introduction of
VLSI technology most ICs had a limited set of functions they could perform. An
electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC
designers add all of these into one chip.

fig 1: A VLSI integrated-circuit diagram.

Developments of VLSI

The first semiconductor chips held two transistors each. Subsequent advances
added more transistors, and as a consequence, more individual functions or systems were
integrated over time. The first integrated circuits held only a few devices, perhaps as
many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate
one or more logic gates on a single device. Now known respectively as small-scale
integration (SSI), improvements in technique led to devices with hundreds of logic gates,
known as medium- scale integration (MSI). Further improvements led to large-scale
integration (LSI), i.e. Systems with at least a thousand logic gates. Current technology has
moved far past this mark and today's microprocessors have many millions of gates and

1
 billions of individual transistors.At one time, there was an effort to name and calibrate
various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration
(ULSI) were used. But the huge number of gates and transistors available on common
devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels
of integration are no longer in widespread use.

In 2008, billion-transistor processors became commercially available. This became

more commonplace as semiconductor fabrication advanced from the then-current generation
of 65 nm processes. Current designs, unlike the earliest devices, use extensive design
automation and automated logic synthesis to layout the transistors, enabling higher levels of
complexity in the resulting logic functionality. Certain high-performance logic blocks like
the SRAM (static random-access memory) cell, are still designed by hand to ensure the
highest efficiency.

fig 2: VLSI Technology design

VLSI DESIGN

VLSI chiefly comprises of Front End Design and Back End design these
days. While front end design includes digital design using HDL, design verification
through simulation and other verification techniques, the design from gates and design
for testability, backend design comprises of CMOS library design and its
characterization. It also covers the physical design and fault simulation.While Simple
logic gates might be considered as SSI devices and multiplexers and parity encoders as
MSI, the world of VLSI is much more diverse. Generally, the entire design procedure
follows a step by step approach in which each design step is followed by simulation
before actually being put onto the hardware or moving on to the next step.
The major design steps are different levels of abstractions of the device as a whole:

2
 Fig 3: VLSI Design Flow.

1.Problem Specification: It is more of a high level representation of the system. The

major parameters considered at this level are performance, functionality, physical
dimensions, and fabrication technology and design techniques. It has to be a tradeoff
between market requirements, the available technology and economical viability of the
design. The end specifications include the size, speed, power and functionality of the
VLSI system.

3
.

2.Architecture Definition: Basic specifications like Floating point units, which

system to use, like RISC (Reduced Instruction Set Computer) or CISC (Complex
Instruction Set Computer), number of ALU‘s cache size etc.

3.Functional Design: Defines the major functional units of the system and hence
facilitates the identification of interconnect requirements between units, the physical
and electrical specifications of each unit. A sort of block diagram is decided upon
with the number of inputs, outputs and timing decided upon without any details of
the internal structure.
4.Logic Design: The actual logic is developed at this level. Boolean expressions,
control flow, word width, register allocation etc. are developed and the outcome is
called a Register Transfer Level (RTL) description. This part is implemented either
with Hardware Descriptive Languages like VHDL and/or Verilog. Gate
minimization techniques are employed to find the simplest, or rather the smallest
most effective implementation of the logic.
5 . Physical Design: The conversion of the net list into its geometrical
representation is done in this step and the result is called a layout. This step follows
some predefined fixed rules like the lambda rules which provide the exact details of
the size, ratio and spacing between components. This step is further divided into
sub-steps which are:
5.1 Circuit Partitioning: Because of the huge number of transistors involved, it is
not possible to handle the entire circuit all at once due to limitations on
computational capabilities and memory requirements. Hence the whole circuit is
broken down into blocks which are interconnected.
5.2 Floor Planning and Placement: Choosing the best layout for each block from
partitioning step and the overall chip, considering the interconnect area between the
blocks, the exact positioning on the chip in order to minimize the area arrangement
while meeting the performance constraints through iterative approach are the major
design steps taken care of in this step.
5.3 Routing: The quality of placement becomes evident only after this step is
completed. Routing involves the completion of the interconnections between
modules. This is completed in two steps. First connections are completed between
blocks without taking into consideration the exact geometric details of each wire and
pin. Then, a detailed routing step completes point to point connections between pins
on the blocks.
5.4 Extraction and Verification: The circuit is extracted from the layout for
4
 comparison with the original net list, performance verification, and reliability
verification and to check the correctness of the layout is done before the final step of
packaging.
6. Fabrication: After layout and verification, the design is ready for fabrication.
Since layout data is typically sent to fabrication on a tape, the event of release of data is
called Tape Out. Layout data is converted (or fractured) into photo-lithographic masks,
one for each layer. Masks identify spaces on the wafer, where certain materials need to be
deposited, diffused or even removed. Silicon crystals are grown and sliced to produce
wafers. Extremely small dimensions of VLSI devices require that the wafers be polished
to near perfection. The fabrication process consists of several steps involving deposition,
and diffusion of various materials on the wafer. During each step one mask is used.
Several dozen masks may be used to complete the fabrication process.
7.Packaging: The chips are put together on a Printed Circuit Board or a Multi Chip
Module to obtain the final finished product.

ADVANTAGES AND DISADVANTAGES OF VLSI:

The number of transistors in an IC has dramatically increased. This led to the
development of VLSI design. An electronic circuit consists of a CPU, RAM, ROM and
other peripherals on one board. VLSI let's all these into one chip resulting in the
following advantages:

● Reduces the size of circuits

● Reduces cost of the devices
● Increases operating speed of circuits
● Less power consumption
● High reliability
● Occupies less area
● Offers lots of employment

The only disadvantage of VLSI is that it has long design and fabrication process and
higher risk.
USES OF VLSI:

● Voice and Data Communication networks

5
 ● Digital Signal Processing
● Computers
● Commercial Electronics
● Automobiles
● Medicine and many more.

APPLICATIONS OF VLSI:

● VLSI is an implementation technology for electronic circuitry – analogue or digital.

● It is concerned with forming a pattern of interconnected switches and gates on
the surfaces of a crystal of semiconductor.
● Microprocessors
- Personal computers
- Microcontrollers
● Memory – DRAM/SRAM.
● Special purpose processors – ASICS (CD players, DSP applications)
● Optical switches

6
 CHAPTER-2

VERILOG

INTRODUCTION:

Verilog is a Hardware Description Language; a textual format for describing

electronic Circuits and systems. Applied to electronic design, Verilog is intended to be
used for Verification through simulation, for timing analysis, for test analysis (testability
analysis and Fault grading) and for logic synthesis.
The Verilog HDL is an IEEE standard - number 1364. The first version of
the IEEE standard For Verilog was published in 1995. A revised version was published
in 2001; this is the Version used by most Verilog users. The IEEE Verilog standard
document is known as the Language Reference Manual or LRM. This is the complete
authoritative definition of the Verilog HDL.
A further revision of the Verilog standard was published in 2005, though it
has little extra compared to the 2001 standard. System Verilog is a huge set of
extensions to Verilog, and was first published as an IEEE standard in 2005
IEEE Std 1364 also defines the Programming Language Interface, or PLI.
This is a collection of software routines which permit a bidirectional interface between
Verilog and other languages (usually C). Note that VHDL is not an abbreviation for
Verilog HDL - Verilog and VHDL are two Different HDLs. They have more similarities
than differences; however.Verilog was started initially as a proprietary hardware
modeling language by Gateway Design Automation Inc. around 1984. It is rumored that
the original language was designed by taking Features from the most popular HDL
language of the time, called Hilo, as well as from Traditional computer languages such
as C. At that time, Verilog was not standardized and the Language modified itself in
almost all the revisions that came out within 1984 to 1990.Verilog Simulator were first
used beginning in 1985 and was extended substantially through 1987. The
implementation was the Verilog simulator sold by Gateway.
The first major extension was Verilog-XL, which added a few features and
implemented the infamous XL algorithm which was a very efficient method for doing
gate-level simulation .The time was late 1990.Cadence Design System, whose primary
product at that time included thin film process simulator, decided to acquire Gateway
Automation System. Along with other gateway products, Cadence now became the
owner of the Verilog language, and continued to market Verilog as both a language and

7
 a simulator. At the same time, Synopsis was marketing the top-down design
methodology, using Verilog. This was a powerful combination.
Individual Aspects of VERILOG:
Capability: Hardware structure can be modeled equally effectively in both VHDL and
Verilog. When modeling abstract hardware, the capability of VHDL can sometimes only be
Achieved in Verilog when using the PLI.
Compilation: The Verilog language is still rooted in its native interpretative mode.
Compilation is a means of speeding up simulation, but has not changed the original nature of
the language. As a result care must be taken with both the compilation order of code written
in a single file and the compilation order of multiple files. Simulation results can change by
simply changing the order of compilation.

Data types: Verilog data types are very simple, easy to use and very much geared
towards modeling hardware structure as opposed to abstract hardware modeling. all data
types used in a Verilog model are defined by the Verilog language and not by the user.
There are net data types, for example wire, and a register data type called reg. A model
with a signal whose type is one of the net data types has a corresponding electrical wire
in the implied modeled circuit. Objects that are signals, of type Reg hold their value over
simulation delta cycles and should not be confused with the modeling of a hardware
register. Verilog may be preferred because of its simplicity.

Design reusability: There is no concept of packages in Verilog. Functions and

procedures used within a model must be defined in the module. To make functions and
Procedures generally accessible from different module statements the functions and
Procedures must be placed in a separate system file and included using the include
Compiler directive.

Easy to Learn: Starting with zero knowledge of either language, Verilog is probably the
easiest to grasp and understand. This assumes the Verilog compiler directive language
for simulation and the PLI language is not included. If these languages are included they
can be looked upon as two additional languages that need to be learned. VHDL may
seem less intuitive at first for two primary reasons. First, it is very strongly typed; a
feature that makes it robust and powerful for the advanced user after a longer learning
phase. Second, there are many ways to model the same circuit, especially those with
large hierarchical structures.

8
 Modeling Styles in VERILOG:
Modeling Style means, that how we Design our Digital IC's in Electronics. With
the help of Modeling style we describe the Design of our Electronics.
Normally we use three type of Modeling Style in Verilog HDL -
1. Data Flow Modeling Style.
2. Gate Modeling Style.
3. Behavior Modeling Style.
1. Data Flow Modeling Style:
Data Flow Modeling Style shows that how the data / Signal flows from input too put
threw the registers / Components. Data Flow Modeling Style Works on Concurrent
Execution.
2. Gate Modeling Style:
Gate Modeling Style shows the Graphical Representation of modules/ instances /
Components with their Interconnection. In Gate Modeling Style We defines that
how our Components / Registers / Modules are connected to each other using Nets/
Wires. Gate Modeling Style works on Concurrent Execution.

3. Gate Modeling Style:

Gate Modeling Style shows the Graphical Representation of modules/
instances / Components with their Interconnection. In Gate Modeling Style We
defines that how our Components / Registers / Modules are connected to each other
using Nets/ Wires. Gate Modeling Style works on Concurrent Execution.

4. Behavior Modeling Style:

Behavior Modeling Style shows that how our system performs according to
current input values. In behavior modeling, we defines that what value we get at the
output corresponding to input values. We define the function / Behavior of our Digital
Systems in Behavior Modeling Style. Behavior Modeling Style works on sequential
execution.

9
 CHAPTER -3

XILINX VIVADO

Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis
of HDL designs, superseding Xilinx ISE with additional features for system on a
chip development and high level synthesis.
Like the later versions of ISE, Vivado includes the in-built logic simulator Vivado also
introduces high-level synthesis, with a tool chain that converts C code into programmable logic.

Features:

Vivado enables developers to synthesize their designs, perform timing analysis

examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target
device with the programmer. Vivado is a design environment for FPGA products from Xilinx,
and is tightly-coupled to the architecture of such chips, and cannot be used with FPGA products
from other vendors.

Vivado was introduced in April 2012, and is an integrated design environment (IDE)
with system-to-IC level tools built on a shared scalable data model and a common debug
environment. Vivado includes electronic system level (ESL) design tools for synthesizing and
verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for
reuse; standards based IP stitching and systems integration of all types of system building blocks;
and the verification of blocks and systems. A free version WebPACK Edition of Vivado
provides designers with a limited version of the design environment.

Components:

The Vivado High-Level Synthesis compiler enables C,C++ and System C programs to
be directly targeted into Xilinx devices without the need to manually create RTL.Vivado HLS is
widely reviewed to increase developer productivity, and is confirmed to support C++ classes,
templates, functions and operator overloading. It is a compiled-language simulator that supports
mixed-language, TCL scripts, encrypted IP and enhanced verification.The Vivado IP
Integrator allows engineers to quickly integrate and configure IP from the large Xilinx IP library.

10
 CHAPTER-4

INTRODUCTION TO FPGA DESIGN FLOW

FPGA:

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured

by a customer or a designer after manufacturing – hence the term field-programmable”. The
FPGA configuration is generally specified using a hardware description language(HDL), similar
to that used for an Application Specific Integrated Circuit(ASIC).

FPGAs contain an array of programmable logic blocks and a hierarchy of "reconfigurable

interconnects" that allow the blocks to be "wired together", like many logic gates that can be
inter- wired in different configurations.Logic blocks can be configured to perform complex
combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, logic
blocks also include memory elements, which may be simple flip flops or more complete blocks
of memory.

FPGA DESIGN FLOW:

This is a simplified/typical design flow.

fig 4:FPGA design flow

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ASIC:

ASIC stands for Application Specific Integrated Circuit. As the name implies, ASICs are
application specific. They are designed for one sole purpose and they function the same their
whole operating life.. Its logic function cannot be changed to anything else because its digital
circuitry is made up of permanently connected gates and flip-flops in silicon.
The logic function of ASIC is specified in a similar way as in the case of FPGAs, using
hardware description languages such as Verilog or VHDL.

ASIC VS FPGA:

FPGA ASIC

Reconfigurable circuit. FPGAs can be Permanent circuitry. Once the application

reconfigured with a different design , the specific circuit is taped-out into silicon, it cannot
circuit is made by connecting a number of be changed.
configurable blocks.

Easier entry-barrier. One can get started Very high entry-barrier in terms of cost, learning
with FPGA development for as low as curve, liaising with semiconductor foundry etc.
2000.. Starting ASIC development from scratch can
cost well into millions of rupees.

Less energy efficient, requires more power Much more power efficient than FPGAs. Power
for same function which ASIC can achieve consumption of ASICs can be very minutely
at lower power. controlled and optimized.

Analog designs are not possible with
FPGAs. Although FPGAs may contain
specific analog hardware such as PLLs,
ADC etc, they are not much flexible to
create. For example RF transceivers.
ASICs can have complete analog circuitry, for
example WiFi transceiver, on the same die along
with microprocessor cores. This is the advantage
which FPGAs lack.

12
 CHAPTER-5
BASIC VERILOG CONCEPTS

MODELING IN VERILOG:

A Module is the basic building block in Verilog ,modules can be interconnected to form a
Digital System, it is like a function in C
MODULE SYNTAX:
module<MODULE NAME><(<port list>)>;
.end module

MODULE NAME:
In place of module name ,we use shift registers, encoders etc..

Port list:

List of all the input and output pins that are needed to be connected like a,b,c,clk,rst,y,op
etc.The main important thing after ever line at the end there must be a semi colon except at the
end module .

PORT DECLARATION:

There are three types of port declarations they are given below :
1 input port
2 output port
3 Bi directional port also known as inout port.

PORT SYNTAX:

module And_gate (A, B, Y); input A, B;

output Y;
.
.
.end module

13
 DATA TYPES:

Nets:
Physical connection between Devices
Reflect logic value of the driving device
Cannot store logic value
eg: wire, tri, wand, wor etc.....only 'wire' net is used

Registers:
Used when data storage is required Retains
previous state value till changed
Does not necessarily imply register or flip-flop or latch, can also imply a wire Denoted
by 'reg'
Integer:
It is a general purpose register used for manipulating quantities.Default width is the host-
machine word size, which will be atleast 32-bits Can be used to store signed values
It is not bit addressable It
can be synthesised

VARIABLE DECLARATION:
These are of three types
1 .Declaring a wire: wire <[<bit range>]> <net_name>; Default width = 1
2 .Declaring a register: reg <[<bit range>]> <reg_name>; Default width = 1
3 .Declaring a memory: reg [<bit range>] <reg_name> [<start_addr>:<end_addr>];
EXAMPLES:

reg r0; // 1 – bit register r0

wire w1, w2; // 1 – bit wires w1 & w2
wire [7:0] a, b; // 8 – bit wires a & b
reg [31:0] counter; // 32 – bit register counter reg [7:0]
RAM_1024_8 [0:1023]; // 1kB memory element RAM
integer
a = 50; // 32 – bit integer declaration
real rval = 3.14; // assigning value to real register
real r1 = 2e6; // assigning 2x10^6 to r1 register
time t1 = $time; // getting simulation time

14
 GATE LEVEL MODELLING:

It is a low level of Abstraction.Circuit is described in terms of primitive gates .Verilog

supports basic logic gates as predefined primitives.Gates can be instantiated like instantiating a
module
There are 2 classes of gates: and/or gates and Buf/not gates
Some of the primitive gates are
AND,NAND
OR,NOR
XOR,XNOR
NOT,BUF.

GATE LEVEL INSTANTIATION:

Syntax:
<Gate> <*delay> <Instance_name>(<o/p variable>,<input variables>);
* Optional, delay will not be synthesised, used only for simulation
purpose

Eg:
and #10 a1(y,a,b); // 2-input And gate with propagation delay 10
not n1(b,a); // Not gate with o/p pin = b, i/p pin = a; Gate // instance= n1

15
 CHAPTER-6

DATA FLOW AND BEHAVIOURAL MODELLING

Number Representation :
Verilog HDL allows integer numbers to be specified as
Syntax: <size>'<radix><value>;
Where,
Size: bit length of value (1,2,3,4-bit, 8, 32,...etc)
Radix: value represented in which format:
a) Bit -> b
b)Hexadecimal -> h
c)Octal -> o
d)Decimal -> d
Value: the value which needs to be assigned

Verilog Operators :

Operators perform an operation on one or more operands within an expression. An expression

combines operands with appropriate operators to produce the desired functional expression.
i) Arithmetic Operators :
ii)Relational Operators
iii)Equality Operators
iv)Logical Operators
v)Reduction Operators
vi)Shift Operators
vii)Concatenation Operator :
Concatenations are expressed using the brace characters { and }, with commas separating the
expressions within.
Example: + {a, b[3:0], c, 4'b1001} // if a and c are 8-bit numbers, the results has 24 bits
Unsized constant numbers are not allowed in concatenations.
viii)Replication Operator:
Replication operator is used to replicate a group of bits n times. Say you have a 4 bit variable
and you want to replicate it 4 times to get a 16 bit variable: then we can use the replication
operator.
Operator description
{n{m}} Replicate value m, n times
16
Repetition multipliers (must be constants) can be used:
{3{a}} // this is equivalent to {a, a, a}
Nested concatenations and replication operator are possible:
{b, {3{c, d}}} // this is equivalent to {b, c, d, c, d, c, d}

ix)Conditional Operator :
The conditional operator has the following C-like format:
<cond_expression> ? <true_expression> : <false_expression>;
The true_expr or the false_expr is evaluated and used as a result depending on what cond_expr
evaluates to (true or false).
Operand Precedence :
Operator symbolsOperator Symbols
Unary, Multiply, Divide, Modulus !, ~, *, /, %
Add, Subtract, Shift +, - , <<, >>
Relation, Equality <,>,<=,>=,==,!=,===,!==
Reduction &, ~&, ^, ^~, |, ~|
Logic &&, ||
Conditional ?:

DATA LEVEL MODELLING:

At this level, the module is defined by defining the data flow.
The designer is aware how the data flows between the hardware registers and the data is
processed in the design.
Continuous Assignment:
A continuous assignment replaces the gates in the description of the circuit and describes the
circuit in a higher level of abstraction.
A continuous assign statement starts with the keyword “assign”
Syntax: assign <variable name> = <expression>;

Example:
module HA_1(sum, c_out,a,b); // Half adder declaration
input a,b; // input ports
output sum,c_out; // output ports
assign sum = a ^ b; // 2-input Xor gate
assign c_out = a & b; // 2-input and gate
endmodule

17
fig 5:logic diagram of Half Adder
BEHAVIOURAL MODELING :
Structured Procedures :
There are two structured procedural assignments in
verilog: initial and always.
All behavioural statements can only appear inside any of these procedural blocks.
All procedural statements are started at time 0 and run parallel in Verilog
However all behavioural statements inside the blocks are executed sequentially.
Each block represents a separate activity flow.
Initial Block :
Initial block starts at exactly time 0.
Executes exactly once during a simulation.
Each block finishes execution independantly, irrespective of other blocks.
This block is not synthesisable.
Always Block :
The always block initiates at time 0
Statements in the always block, execute in a continuous loop fashion
Used to model a block of activity which is repeated continuouly in a digital circuit.
Synthesisability of this block is dependant on the statements present within this block.
Syntax :
Initial block:
initial begin
....
.
....
end
Always block:
always @(<event_list>) begin
.....
...
end
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Event list: Denotes the variables which determine when and how theregister values used in the
procedural block change.
Eg: For sequential circuits, event list will consist of clock pin and reset pin.
Blocking statements:
Blocking statements are executed in the order they are specified in the order they are specified in
the sequential block. Only after the blocking assignment has finished executing will it allow the
next in strict in the block to execute.
Syntax:
Initial begin
..
a = 4'b0010; // blocking statement
x = a + x;
...
end
Non-Blocking statements:
Non-Blocking statements allow the execution of the statements that follow in the sequential
block.
Syntax:
initial begin
..
a <= 4'b0010; // non-blocking
x <= a + x; // statement
...
End
If Statement :
Syntax:
if (expression)
begin
...statements...
end
else if (expression)
begin
...statements...
end
...more else if blocks
else
begin
...statements...
end

19
Example:
if (alu_func == 2'b00)
aluout = a + b;
else if (alu_func == 2'b01)
aluout = a – b;
else if (alu_func == 2'b10)
aluout = a & b;
Case Statement:
Syntax:
case (expression)
case_choice1:
begin
...statements...
end
case_choice2:
begin
...statements...
end
...more case choices blocks...
Default:
begin
...statements...
End
endcase
Example:
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
Default: out = 0;
Endcase
For Statement:
Syntax:
for(<initial_assignment>,<condition>,<step_assignment>)
begin
<statements>;
...
end

20
Example:
for (i = 2'b0; i <= 2'b11; i = i + 2'b01)
#10 y = y + 8'h01;
While Statement :
Syntax:
while (<expression>)
begin
<statements>;
...
end
Example:
while (i < 3) begin
#10 Y = Y + 1;
i = i + 1;
end
Repeat and Forever Loop:
Syntax:
repeat (<number of times>)
begin
...
end
Example:
repeat (4) #10 Y = Y + 1;

21
 CHAPTER-7

COMBINATIONAL CIRCUITS

In digital circuit theory, combinational logic (sometimes also referred to as time-independent

logic) is a type of digital logic which is implemented by Boolean circuits, where the output is
a pure function of the present input only. This is in contrast to sequential logic, in which the
output depends not only on the present input but also on the history of the input. In other words,
sequential logic has memory while combinational logic does not.
Combinational logic is used in computer circuits to perform Boolean algebra on input signals and
on stored data. Practical computer circuits normally contain a mixture of combinational and
sequential logic. For example, the part of an arithmetic logic unit, or ALU, that does
mathematical calculations is constructed using combinational logic. Other circuits used in
computers, such as half adders, full adders, half subtractors, full
subtractors, multiplexers, demultiplexers, encoders and decoders are also made by using
combinational logic
TYPES OF COMBINATIONAL CIRCUIT:

fig 6:block diagram of types of combinational circuit

MULTIPLEXER:
In electronics, a multiplexer (or mux) is a device that selects between several analog
or digital input signals and forwards it to a single output line. A multiplexer of inputs
22
has select lines, which are used to select which input line to send to the output. Multiplexers are
mainly used to increase the amount of data that can be sent over the network within a certain
amount of time and bandwidth. A multiplexer is also called a data selector. Multiplexers can also
be used to implement Boolean functions of multiple variables.
BLOCK DIAGRAM:

m-to-1 ( m = 2^n) multiplexers

fig 7:multiplexer without enable and with enable

BEHAVIORAL 4-BIT MULTIPLEXER VERILOG CODE:

module mux4( input a, b, c, d ,input [1:0] sel, output out );
reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule

23
DEMULTIPLEXER:
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of
several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input. A demultiplexer is also called a data
distributor.Demultiplexers can be used to implement general purpose logic. By setting the input
to true, the demux behaves as a decoder.
BLOCK DIAGRAM:
1-to-m ( m = 2^n ) demultiplexers

Fig 8: demultiplexer with enable

n-bit 1-to-4 demultiplexer

example:
// an N-bit 1-to-4 demultiplexer
using if ... else structure
parameter N = 4; // default
width
input [1:0] select;
input [N-1:0] in;
output reg [N-1:0] y3, y2, y1, y0;
always @(select or in) begin
if (select == 3) y3 = in; else y3 = {N{1'b0}};
if (select == 2) y2 = in; else y2 = {N{1'b0}};
if (select == 1) y1 = in; else y1 = {N{1'b0}};
if (select == 0) y0 = in; else y0 = {N{1'b0}};
end

24
 DECODER:
The name “Decoder” means to translate or decode coded information from one format into
another, so a digital decoder transforms a set of digital input signals into an equivalent
decimal code at its output. A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2^n unique output lines.

fig 9:logic symbol,function table and logic circuit of decoder

A 2 to 4 decoder with active low output:

always @(x or enable_n)

if (enable_n) y = 4'b1111; else case (x)

2'b00 : y = 4'b1110;
2'b01 : y = 4'b1101;
2'b10 : y = 4'b1011;
2'b11 : y = 4'b0111;
endcase

25
ENCODER:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and 'n' output lines. It will produce a binary code equivalent to the
input, which is active High. Therefore, the encoder encodes 2n input lines with 'n' bits.
BLOCK DIAGRAM:
m= 2^n

A 4 to 2 encoder example:

fig 10:function table and logic circuit of encoder

Fig 11:encoder with enable and with noninverted and inverted outputs

26
example program:
// a 4-to-2 encoder using if ... else structure
module enco_1(input [3:0]in,input e,output
reg [1:0]y);
always@(*)
begin
if(e)
begin
case(in)
4’b0001:y=0;
4’b0010:y=1;
4’b0100:y=2;
4’b1000:y=3;
default:y=2’bxx;
endcase;
end
else
y=2’bxx;
end
endmodule

Code converters:
A code converter is a circuit that one form of coded

information to another form of coded information.

Some of the examples are

Binary to gray,binary to excess 3,……..

Binary to gray:

This converts binary code to gray code. The gray code is a non-weighted code because
there is no particular weight is assigned for the position of the bit. A n-bit code can be attained
by reproducing a n-1 bit code on an axis subsequent to the rows of 2n-1, as well as placing the
most significant bit of 0 over the axis with the most significant bit of 1 beneath the axis.

27
 The step by step gray code generation is as shown

fig 12 :logic circuit and truth table for binary to gray converter

Binary to BCD:

This converts binary code to excess 3 code. BCD is binary coded decimal number, where
each digit of a decimal number is respected by its equivalent binary number. That means, LSB of
a decimal number is represented by its equivalent binary number and similarly other higher
significant bits of decimal number are also represented by their equivalent numbers.

fig 13:truth table for binary to BCD converter

28
 BCD to 7 segment:

This converts BCD code to 7 segment code.A BCD to Seven Segment decoder is a
combinational logic circuit that accepts a decimal digit in BCD (input) and generates appropriate
outputs for the segments to display the input decimal digit.

fig 14:truth table for BCD to 7 segment converter.

29
 CHAPTER-8

SEQUENTIAL CIRCUIT DESIGN

Sequential circuits are digital circuits in which the outputs depend not only on the current inputs,
but also on the previous state of the output.
The basic sequential circuit elements can be divided in two categories
– Level-sensitive (Latches)
High-level sensitive
Low-level sensitive
– Edge-triggered (Flip-flops)
Rising (positive) edge triggered
Falling (negative) edge triggered
Dual-edge triggered
Set/Reset (SR) Latch:

The Set/Reset latch is the most basic unit of sequential digital circuits.The S input sets the
Q output to a logic 1 and the R input resets the Q output to a logic 0

Gated SR Latch:

To be able to control when the S and R inputs of the SR latch can be applied to
the latch and thus change the outputs, an extra input is used (Enable). If the
Enable is 0 then the S and R inputs have no effect on the outputs of the SR latch.
If the Enable is 1 then the Gated SR latch behaves as a normal SR latch.
D Latch:

A problem with the SR latch is that the S and R inputs can not be at logic 1 at the same
time. To ensure that this can not happen, the S and R inputs can by connected through an
inverter.
In this case the Q output is always the same as the input, and the latch is called the Data
or D latch.The D latch is used in Registers and memory devices

30
 JK Latch:

Another way to ensure that the S and R inputs can not be at logic 1 simultaneously, is to
cross connect the Q and Q’ outputs with the S and R inputs through AND gates. The latch
obtained is called the JK latch.In the J and K inputs are both 1 then the Q output will change
state (Toggle) for as long as the Enable 1, thus the output will be unstable.This problem is
avoided by ensuring that the Enable is at logic 1 only for a very short time, using edge detection
circuits.

Latches and Flip-Flops:

Latches are called level triggered data elements, because the change on the outputs will
follow the changes of the inputs as long as the Enable input is set. Flip-Flops are called edge
triggered data elements, because the change on outputs occur only at the transition of the clock.
JK Flip-Flop:

The JK edge triggered flip flop can be obtained by inserting an edge detection circuit at
the Enable (CLK) input of a JK latch.This ensures that the outputs of the flip flop will
change only when the CLK changes (0 to 1 for +ve edge or 1 to 0 for –ve edge)

D (Data) Flip-Flop:

The D flip-flop can be obtained by connecting the J with the K inputs of a JK flip-flop
through an inverter.The D flip-flop can also be obtained by connecting the S with the R
inputs of a SR flip-flop through an inverter
T (Toggle)Flip-Flop:

The T edge triggered flip flop can be obtained by connecting the J with the K inputs of a
JK flip directly.When T is zero then both J and K are zero and the Q output does not
change. When T is one then both J and K are one and the Q output will change to the
opposite state, or toggle.

Data Register with 4 Flip-Flops and Asyncreset :

module register( din, clk, rst_n, qout );
parameter N = 4;
input [N-1:0] din;
input clk, rst_n;
output reg [N-1:0] qout; always @ (posedge clk, negedge rst_n)
if (!rst_n) qout <= { N {1'b0} };
else qout <= din;
endmodule

31
Blocking vs Non-Blocking Assignments:

// using Non-Blocking ( <= )

module syncgood( input clk, d,

output reg q);

reg n1;

always @(posedge clk) begin

n1 <= d; // nonblocking

q <= n1; // nonblocking

end

endmodule

// using Blocking ( = )

module syncbad( input clk, d,

output reg q);

regn1; always @(posedge clk) begin

n1 = d; // blocking

q = n1; //blocking

end

endmodule

32
 CHAPTER-9

SEQUENTIAL CIRCUIT DESIGN-II

In digital circuits, a shift register is a cascade of flipflops, sharing the

same clock, in which the output of each flip-flop is connected to the "data" input of the next
flip-flop in the chain, resulting in a circuit that shifts by one position the "bit array" stored in
it, "shifting in" the data present at its input and 'shifting out' the last bit in the array, at each
transition of the clock input.

UNIVERSAL SHIFT REGISTER:

Universal Shift Register is a register which can be configured to load and/or retrieve the data
in any mode (either serial or parallel) by shifting it either towards right or towards left. In
other words, a combined design of unidirectional (either right- or left-shift of data bits as in
case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load
provision is referred to as universal shift register. Such a shift register capable of storing n
input bits is shown

Fig12:Universal shift register

VERILOG CODE FOR UNIVERSAL SHIFT REGISTER:

module universal_shift_reg

#(parameter N=8)

(input clk,rts,lsi,rsi,input [1:0]din,output [N-1:0]qout);

reg [N-1:0] r_reg,r_next;

always @(posedge clk,posedge rst)

if(rst)

r_reg<={N{1’b0}};

33
else

r_reg<=r_next;

always @* case(ctrl)

2’b00:r_next=r_reg;

2’b01:r_next={lsi,r_reg[N-1:1]};

2’b10:r_next={r_reg[N-2:0],rsi};

default:r_next=din;

endcase

assign qout=r_reg;

endmodule

COUNTERS:

A counter circuit is usually constructed of a number of flipflops connected in cascade.

Counters are a very widely used component in digital circuits, and are manufactured as
separate integrated circuits and also incorporated as parts of larger integrated circuits.

Types of counters:

1.Asynchronous

2.Synchronous

Asynchronous (ripple) counters are

a)Binary counter (up/down counters)
Synchronous counters are

a) Binary counter (up/down counters)

b) BCD counter (up/down counters)

c) Gray counters (up/down counters)

34
BINARY RIPPLE COUNTER:

A counter that follows the binary sequence is called a binary counter. A binary
ripple counter consists of a series of complementing flip flops (T or JK FF) with the output of
each flip flop connected to the clock pulse input of the next higher order flip flop

UNIVERSAL BINARY COUNTER:

Bidirectional counters are capable of counting in either the up direction or the down
direction through any given count sequence.As well as counting “up” from zero and increasing
or incrementing to some preset value, it is sometimes necessary to count “down” from a
predetermined value to zero allowing us to produce an output that activates when the zero count
or some other pre-set value is reached.

fig 15:logic diagram and truth table for universal binary counter

35
36
SPECIAL COUNTERS:

RING COUNTER:

A ring counter is a type of counter composed of flip flops connected into a shift register,
with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring"
structure.So on each successive clock pulse, the counter circulates the same data bit between the
four flip-flops over and over again around the “ring” every fourth clock cycle. But in order to
cycle the data correctly around the counter we must first “load” the counter with a suitable data
pattern as all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring
counter invalid.

Fig13:Ring counter

4-Bit Ring counter:

Verilog code:
module ring_counter(clk,rst,count_out);
input clk;
input rst;
iutput [3:0] count_out;
reg [3:0] count_temp;
always@(posedge clk,rst)
begin
if(rst==1’b1)
count_temp=4’b0001;
else if(clk==1’b1)
count_temp=(count_temp[2:0],count_temp[3]);
end

37
 assign count_out=count_temp;
endmodule
Testbench:
module tb_ring;
reg clk;
reg rst;
wire [3:0] count_out;
ring_counter uut(.clk(clk),.rst(rst),.count_out(count_out));
initial clk=0;
a;lways #10 clk=~clk;
initial begin
rst =1;
#50;
rst=0;
end
endmodule
JOHNSON COUNTER:

Johnson counter also known as creeping counter, is an example of synchronous counter.

In Johnson counter, the complemented output of last flip flop is connected to input of first flip
flop and to implement n-bit Johnson counter we require n flip-flop.The Johnson Ring Counter or
“Twisted Ring Counters”, is another shift register with feedback exactly the same as the
standard Ring Counter above, except that this time the inverted output Q of the last flip-flop is
now connected back to the input D of the first flip-flop as shown below.

Fig15:Johnson counter

38
The main advantage of this type of ring counter is that it only needs half the number of flip-flops
compared to the standard ring counter then its modulo number is halved. So a “n-stage” Johnson
counter will circulate a single data bit giving sequence of 2n different states and can therefore be
considered as a “mod-2n counter.

Verilog code:

module ring_counter{
clk;
rst;
count_out;
);
input clk;
input rst;
iutput [3:0] count_out;
reg [3:0] count_temp;
always@(posedge clk,rst)
begin
if(rst==1’b1)
count_temp=4’b0001;
else if(clk==1’b1)
count_temp=(count_temp[2:0],count_temp[3]);
end
assign count_out=count_temp;
endmodule
Testbench:
module tb_ring;
reg clk;
reg rst;
wire [3:0] count_out;
ring_counter uut(.clk(clk),.rst(rst),.count_out(count_out));

39
initial clk=0;
a;lways #10 clk=~clk;
initial begin
rst =1;
#50;
rst=0;
end
endmodule

40
 CHAPTER 10

FINITE STATE MACHINES

Finite State Machine:

A Finite State Machine (FSM) is used to model a system that transits among finite number of
internal states .The transitions depend on the current state and external inputs. Unlike a
regular sequential circuit, the state transitions of an FSM do not exhibit a simple repetitive
pattern – Its next state logic is usually constructed from scratch and is sometimes known as
“random logic”.
All FSMs have a general feedback structure consisting of the following :
Combinational logic calculated the next state value and State registers hold the value of the
present state.
A synchronous sequential circuit is also called as Finite State Machine(FSM), if it has finite
number of states. There are two types of FSMs.
● Mealy State Machine
● Moore State Machine
Mealy State Machine:
The block diagram of Mealy state machine is shown in the following figure

fig 16:block diagram for mealy state machine

41
As shown in figure, there are two parts present in Mealy state machine. Those are
combinational logic and memory. Memory is useful to provide some or part of previous
outputs (present states) as inputs of combinational logic.
So, based on the present inputs and present states, the Mealy state machine produces outputs.
Therefore, the outputs will be valid only at positive (or negative) transition of the clock signal.
Next state and Outputs depend on present state and present input
– ns(t) = f1(cs(t), ip(t)) – op(t) = f2(cs(t), ip(t))
The state diagram of Mealy state machine is shown in the following figure.

Fig:state diagram for Mealy state machine

In the above figure, there are three states, namely A, B & C. These states are labelled inside the
circles & each circle corresponds to one state. Transitions between these states are represented
with directed lines. Here, 0 / 0, 1 / 0 & 1 / 1 denotes input / output. In the above figure, there are
two transitions from each state based on the value of input, x.
In general, the number of states required in Mealy state machine is less than or equal to the
number of states required in Moore state machine. There is an equivalent Moore state machine
for each Mealy state machine.

Moore State Machine:

A Finite State Machine is said to be Moore state machine, if outputs depend only on present
states. The block diagram of Moore state machine is shown in the following figure.
– ns(t) = f1(cs(t), ip(t))
– op(t) = f2(cs(t))

42
 fig 17:Block diagram for moore state machine
As shown in figure, there are two parts present in Moore state machine. Those are combinational
logic and memory. In this case, the present inputs and present states determine the next states.
So, based on next states, Moore state machine produces the outputs. Therefore, the outputs will
be valid only after transition of the state.

Fig:State diagram for Moore state machine

In the above figure, there are four states, namely A, B, C & D. These states and the respective
outputs are labelled inside the circles. Here, only the input value is labeled on each transition. In
the above figure, there are two transitions from each state based on the value of input, x.
In general, the number of states required in Moore state machine is more than or equal to the
number of states required in Mealy state machine. There is an equivalent Mealy state machine
for each Moore state machine. So, based on the requirement we can use one of them.
State Encoding:
In a FSM design each state is represented by a binary code, which are used to identify the state
of the machine. These codes are the possible values of the state register. The process of
assigning the binary codes to each state is known as state encoding.
The choice of encoding plays a key role in the FSM design. It influences the complexicity, size,
power consumption, speed of the design. If the encoding is such that the transistors of flip-flops

43
are minimized then the power will be saved. The timing of the machine are often affected by the
choice of encoding.
State Encoding Techniques:
The following are the most common state encoding techniques used.
Binary encoding,One-hot encoding and Gray encoding.
In the following assume that there are N number of states in the FSM.
Binary encoding:
The code of a state is simply a binary number. The number of bits is equal to log2(N) rounded to
next natural number. Suppose N=6, the number of bits are 3, and the state codes are:
S0-000
S1-001
S2-010
S3-011
S4-100
S5-101

One-hot encoding:
In One-hot encoding only one bit of state vector is asserted for any given state. All other state
bits are zero. Thus if there are N states then N flip-flops are required. As only one bit remains
high and rest are logic low, it is called as One-hot encoding. If N=5, then the number of bits
required are 5, and the state codes are:
S0-00001
S1-00010
S2-00100
S3-01000
S4-10000
Gray Encoding:
Gray encoding uses the Gray codes, also known as reflected binary codes, to reach states, where
two successive codes differ in only one digit. This helps in reducing the number of transition of

44
flip-flops outputs. The number of bits is equal to log2(N) rounded to next natural number. If
N=4, then 2 flip-flops are required and the state codes are:
S0-00
S1-01
S2-11
S3-10
Verilog code for 1101 FSM:
module fsm1101(
input x,
input clk,
input rst,
output y
);
localparam s0=3’b000;
localparam s1=3’b001;
localparam s2=3’b010;
localparam s3=3’b011;
localparam s4=3’b100;
reg [2:0] state_reg, state_next;
always@(posedge clk,posedge rst)
begin
if(rst)
state_reg<=s0;
else
state_reg<=state_next;
end
always@(*)
begin
45
case(state_reg)
s0:state_next=x?s1:s0;
s1:state_next=x?s2:s0;
s2:state_next=x?s2:s3;
s3:state_next=x?s4:s0;
s4:state_next=x?s2:s0;
default:state_next=s0;
endcase
end
assign y=(state_reg==s4);
endmodule

fig 18:FSMD block diagram

● The conceptual block diagram of FSMD is divided into data path and control path.
● The data path consists of the following
− Data registers
− Functional units
46
 − Routing network
● The data path follows the control signal to perform desired operations.

Control Path:

● The control path is a regular FSM with:

− State register
− Next state logic
− Output logic
● It uses external command signal and data path status signal to generate control signal
for the data path.
● It also generates external status signals.

47
 CHAPTER-11
CONCLUSION

In this Internship, we have learnt how to use basic commands in Xilinx software
and how one can built a microprocessor using Hardware Description Language. The
combinational circuits like encoder, decoder, multiplexer etc..and sequential circuits like
latches, flipflops, counters, etc.. can be realised first in order to build a microprocessor by
Xilinx software. We also learnt the key stages in Hardware Description Language(HDL)
based on Field Programmable Gate Array and how it presents the real world designs like
UART,timersetc.. This can be achieved by using Finite State Machine.

The Finite State Machine(FSM) is an abstract mathematical model of a sequential

logic function. Mealy and Moore FSMs are the main two types of FSM which are used to
design any hardware components. An FSM can change the output from one state to another
state in response to some external inputs, the change from one state to another is called
transition.

After achieving the output from FSM , the code which was realised is synthesized
and was dumped into the microprocessor to get the desired 8-bit, 16-bit, 32-bit or 64-bit
microprocessors.

48
 REFERENCES

1) Dr. Esam Al-Qaralleh, “Introduction to Verilog Hardware Description Language”,

Princess Sumaya , University for Technology.
2) Thanasis Oikonomou, “Verilog HDL Basics,” Computer Science Department, University
of Crete,Greece, October 1998.
3) Samir Palnitkar, “Verilog HDL, A guide to digital design and synthesis”, Prentice Hall
Professional,2nd Edition
4) StevePoret,RCS,deimos.eos.uoguelph.ca/.../ENG6530-StevePoret-PaperReview2008.ppt
5) Samir Palnitkar, “Verilog HDL, A guide to digital design and synthesis”, Prentice
HallProfessional, 2nd Edition.
6) M. Morris Mano, Michael D. Ciletti, “Digital Design”, Pearson (2008), 4th Edition.
7) Pong P Chu, “FPGA Prototyping Using Verilog Examples: Xilinx Spartan-3
Version”,Wiley-Interscience, 1st Edition .
8) Ming-Bo Lin, Digital System Designs and practices : using verilog HDL and
FPGAs,Wiley publishing @ 2008.
9) Mark Gordon Arnold,Verilog Digital Computer Design: Algorithms in to hardware,
Prentice-Hall,jnc.upper saddle river,NJ,USA @1998.

49