VLSI DESIGN

Submitted to
Chhattisgarh Swami Vivekanand Technical University Bhilai (C.G.)
In partial fulfilment for award of degree
Of

BACHELOR OF TECHNOLOGY
In
Electronics & Telecommunication Engineering
By

NILESH
(Roll No-300802819039)
Semester-7th
________________________________________________________________
___

Department of Electronics and Telecommunication Engineering

Jhada Siraha Govt. Engineering college Jagdalpur Bastar,(c.g.)

Session 2022-2023
__________________________________________________
__
Page
CERTIFICATE OF TRAINING:-

Page
Chapter 1 INTRODUCTION TO VLSI SYSTEMS

Historical Perspective:
The electronics industry has achieved a phenomenal growth over the last two decades, mainly
due to the rapid advances in integration technologies, large-scale systems design - in short, due
to the advent of VLSI. The number of applications of integrated circuits in high-performance
computing, telecommunications, and consumer electronics has been rising steadily, and at a very
fast pace. Typically, the required computational power (or, in other words, the intelligence) of
these applications is the driving force for the fast development of this field.

The current leading-edge technologies (such as low bit-rate video and cellular communications)
already provide the end-users a certain amount of processing power and portability. This trend is
expected to continue, with very important implications on VLSI and systems design. One of the
most important characteristics of information services is their increasing need for very high
processing power and bandwidth (in order to handle real-time video, for example). The other
important characteristic is that the information services tend to become more and more
personalized (as opposed to collective services such as broadcasting), which means that the
devices must be more intelligent to answer individual demands, and at the same time they must
be portable to allow more flexibility/mobility. At that time, a minimum feature size of 0.3
microns was expected around the year 2000. The actual development of the technology,
however, has far exceeded these expectations. A minimum size of 0.25 microns was readily
achievable by the year 1995. As a direct result of this, the integration density has also exceeded
previous expectations - the first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip
containing more than 3 million transistors were already available by 1994, pushing the envelope
of integration density.

VLSI design Flow:

Figure-1.1: A more simplified view of VLSI design flow.

Figure 1.1 provides a more simplified view of the VLSI design flow, taking into account the
various representations, or abstractions of design - behavioral, logic, circuit and mask layout.
Page
Note that the verification of design plays a very important role in every step during this process.
The failure to properly verify a design in its early phases typically causes significant and
expensive re-design at a later stage, which ultimately increases the time-to-market.

VLSI Design Styles:

Several design styles can be considered for chip implementation of specified algorithms or logic
functions. Each design style has its own merits and shortcomings, and thus a proper choice has to
be made by designers in order to provide the functionality at low cost.

Field Programmable Gate Array (FPGA)

Fully fabricated FPGA chips containing thousands of logic gates or even more, with
programmable interconnects, are available to users for their custom hardware programming to
realize desired functionality. This design style provides a means for fast prototyping and also for
cost-effective chip design, especially for low-volume applications. A typical field programmable
gate array (FPGA) chip consists of I/O buffers, an array of configurable logic blocks (CLBs),
and programmable interconnect structures. The programming of interconnects is implemented by
programming of RAM cells whose output terminals are connected to the gates of MOS pass
transistors. A general architecture of FPGA from XILINX is shown in Fig. 1.12. A more detailed
view showing the locations of switch matrices used for interconnect routing is given in Fig. 1.13.
A simple CLB (model XC2000 from XILINX) is shown in Fig. 1.14. It consists of four signal
input terminals (A, B, C, D), a clock signal terminal, user-programmable multiplexers, an
SRlatch, and a look-up table (LUT). The LUT is a digital memory that stores the truth table of
the Boolean function. Thus, it can generate any function of up to four variables or any two
functions of three variables. The control terminals of multiplexers are not shown explicitly in
Fig. 1.14.
The CLB is configured such that many different logic functions can be realized by programming
its array. The typical design flow of an FPGA chip starts with the behavioral description of its
functionality, using a hardware description language such as VHDL. The synthesized
architecture is then technology-mapped (or partitioned) into circuits or logic cells. At this stage,
the chip design is completely described in terms of available logic cells. Next, the placement and
routing step assigns individual logic cells to FPGA sites (CLBs) and determines the routing
patterns among the cells in accordance with the netlist. Page
 Figure-1.2: General architecture of Xilinx FPGAs.

performance of the design can be simulated and verified before downloading the design for
programming of the FPGA chip. The programming of the chip remains valid as long as the chip
is powered-on, or until new programming is done. In most cases, full utilization of the FPGA
chip area is not possible - many cell sites may remain unused.
The largest advantage of FPGA-based design is the very short turn-around time, i.e., the time
required from the start of the design process until a functional chip is available. Since no
physical manufacturing step is necessary for customizing the FPGA chip, a functional sample
can be obtained almost as soon as the design is mapped into a specific technology. The typical
price of FPGA chips are usually higher than other realization alternatives (such as gate array or
standard cells) of the same design, but for small-volume production of ASIC chips and for fast
prototyping, FPGA offers a very valuable option.

Full Custom Design

Although the standard-cells based design is often called full custom design, in a strict sense, it is
somewhat less than fully custom since the cells are pre-designed for general use and the same
cells are utilized in many different chip designs. In a fuller custom design, the entire mask design
is done anew without use of any library. However, the development cost of such a design style is
becoming prohibitively high. Thus, the concept of design reuse is becoming popular in order to
reduce design cycle time and development cost. The most rigorous full custom design can be the
design of a memory cell, be it static or dynamic. Since the same layout design is replicated, there
Page
would not be any alternative to high density memory chip design. For logic chip design, a good
compromise can be achieved by using a combination of different design styles on the same chip,
such as standard cells, data-path cells and PLAs. In real full-custom layout in which the
geometry, orientation and placement of every transistor is done individually by the designer,
design productivity is usually very low - typically 10 to 20 transistors per day, per designer.
In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions
to this include the design of high-volume products such as memory chips, high- performance
microprocessors and FPGA masters.

Fig: Impact of different VLSI design styles on design cycle time & achievable chip performance.

Chapter 2

Hardware Description Language

Aspects of Hardware Description:

There are two fundamental aspects of any piece of hardware:

# Behavioral.
# Structural.
Page
The behavioral aspect deals with the behavior of hardware: what is its functionality and speed
(without worrying about the constructional details).

The structural aspect tells us about the hardware construction: which parts have been selected for
construction and how they have been interconnected.

Of course, complete information on the hardware requires a combination of both the behavioral
and structural aspects. However, in many practical situations, we may need to focus only on a
single aspect.
Besides the behavioral (functionality and timing) and structural (net list) aspects, there is also a
third aspect to a hardware. This is the physical aspect (e.g. the layout of the IC or the PCB). In
fact the information on each of these aspects is itself represented at different levels of detail,
using different abstraction levels. Each abstraction level is used to represent information on an
aspect of the design at a certain convenient level of detail.
For example, the structural aspect (the net list) of a VLSI design can be described at several
different abstraction levels e.g. the system structure level, the processor-buses level, the
ALUregister level, the gate ip/op level, and the transistor level. Simultaneously, the behavioral
and physical aspects of a VLSI chip/system can also be described at different levels of
abstraction. Very often the three aspects of a design are called the three design domains. And for
each domain (aspect) there are several different levels of abstraction at which the design
information in that domain is represented.
Therefore, a complete system of maintaining, providing, and exchanging information on a VLSI
design must address all the three domains (aspects) individually or in combination. However, a
single design description language that permits design description in all the three design domains
at each of the abstraction levels does not exist.

Hardware description languages (HDLs) have been developed to provide a means of describing,
validating, maintaining and exchanging design information on complex digital VLSI chips across
multiple levels of design abstractions used during the design process in behavioral and structural
domains.

Advantages of HDL-Based Design Approach:

# Specifications captured using HDLs are easier to understand, less error prone, and can be modified
easily.
# HDL descriptions are faster to simulate.
# Design of complex systems is easier.
# It results in a shorter design cycle.
Page
Disadvantages of HDL-Based Design Approach:

# only a subset of the HDL constructs can be synthesized.

# the resulting hardware is generally greater than the optimum.

Specifying Logic:

How do we specify logic?

1. through Boolean Expressions.

Y = (A.B' + B.C.D). (C' + A')

2. through Truth Tables.

3. through Natural Language Statements.

4. through Programming Language Statements.

(C, C++, Pascal, Basic, FORTRAN)

5. Through Behavioral Description Constructs of Hardware Description Languages (VHDL,

Verilog) e.g. process statement in VHDL.

Implementing Logic:

How do you efficiently implement logic given the constraints on-

# Speed of Operation.
# Power Consumption.
# Area.
# Design Time. #
Design Cost.
# Product Cost.
# Upgradability.
The strategic planning and selection of an optimal approach for implementation of
logic is typically called architecting or architecture design.
Page
Specifying and Implementing Logic:

Example Logic Specification: Z = A + B + C + D + E

Architecture #1 (Combinational) for Logic Implementation

Architecture #2 (Combinational) for Logic Implementation

Architecture #3 (Sequential) for Logic Implementation

Page
Sequential Architectures:

Characteristics of Sequential Architectures:

# They need storage elements besides combinational logic.

# They need a sequence of steps to implement the full logic specification.
#Next step should be taken only when the logic function of the previous step has been completed
and its result saved.
# the stepping can be asynchronous/self-timed/synchronous (with timing signal called clock).
# depending upon the selection of method of stepping, sequential architectures can be
asynchronous/self-timed/synchronous.

Chapter 3 VHDL
Introduction:
VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for
Very High Speed Integrated Circuits). It is a hardware description language that can be used to
model a digital system at many levels of abstraction ranging from the algorithmic level to the
gate level. The complexity of the digital system being modeled could vary from that of a simple
gate to a complete digital electronic system, or anything in between. The digital system can also
be described hierarchically. Timing can also be explicitly modeled in the same description.

The VHDL language can be regarded as an integrated amalgamation of the following languages:
sequential language +
Page
 concurrent language + net-list
language +
timing specifications + waveform
generation language => VHDL

Therefore, the language has constructs that enable you to express the concurrent or sequential
behavior of a digital system with or without timing. It also allows you to model the system as an
interconnection of components. Test waveforms can also be generated using the same constructs.
All the above constructs may be combined to provide a comprehensive description of the system
in a single model.
The language not only defines the syntax but also defines very clear simulation semantics for
each language construct. Therefore, models written in this language can be verified using a
VHDL simulator.

Capabilities:
The following are the major capabilities that the language provides along with the features that
differentiate it from other hardware description languages.

• The language supports flexible design methodologies: top-down, bottom-up, or mixed.

• It supports both synchronous and asynchronous timing models.
• The language supports three basic different description styles: structural, dataflow, and
behavioral. A design may also be expressed in any combination of these three descriptive
styles.
• The language has elements that make large scale design modeling easier, for example,
components, functions, procedures, and packages.
• Models written in this language can be verified by simulation since precise simulation
semantics are defined for each language construct.

Basic Terminologies:
VHDL is a hardware description language that can be used to model a digital system. The digital
system can be as simple as a logic gate or as complex as a complete electronic system. A
hardware abstraction of this digital system is called an entity in this text. An entity X, when used
in another entity Y, becomes a component for the entity Y. Therefore, a component is also an
entity, depending on the level at which you are trying to model.
To describe an entity, VHDL provides five different types of primary constructs, called" design
units. They are-
1. Entity declaration
2. Architecture body
Page
 3. Configuration declaration
4. Package declaration
5. Package body

1. Entity Declaration
The entity' declaration specifies the name of the entity being modeled and lists the set of interface
ports. Ports are signals through which the entity communicates with the other models in its
external environment.

Here is an example of an entity declaration for the half-adder circuit shown in Fig. 2.3.
entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT); end
HALF_ADDER;

2. Architecture Body (modeling style in Verilog HDL)

The internal details of an entity are specified by an architecture body using any of the following
modeling styles:

a. Structural style of modeling- As a set of interconnected components

b. Dataflow style of modeling- As a set of concurrent assignment statements
c. Behavioral style of modeling- As a set of sequential assignment statements
d. Mixed style of modeling- Any combination of the above three.

a. Structural Style of Modeling

In the structural style of modeling, an entity is described as a set of interconnected components.

Such a model for the HALF_ADDER entity, shown in Fig. 2.3, is described in an architecture
body as shown below-

architecture HA_STRUCTURE of HALF_ADDER is component

XOR2
port (X, Y: in BIT; Z: out BIT);
end component; component AND2
port (L, M: in BIT; N: out BIT);
Page
end component; begin
X1: XOR2 port map (A, B, SUM); A1:
AND2 port map (A, B, CARRY); end
HA_STRUCTURE;

The name of the architecture body is HA_STRUCTURE. The entity declaration for
HALF_ADDER (presented in the previous section) specifies the interface ports for this
architecture body. The architecture body is composed of two parts: the declarative part (before
the keyword begin) and the statement part (after the keyword begin). Two component
declarations are present in the declarative part of the architecture body. These declarations
specify the interface of components that are used in the architecture body. The components
XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they
may later be bound to other components in a library.

b. Dataflow Style of Modeling

In this modeling style, the flow of data through the entity is expressed primarily using concurrent
signal assignment statements. The structure of the entity is not explicitly specified in this
modeling style, but it can be implicitly deduced. Consider the following alternate architecture
body for the HALF..ADDER entity that uses this style.

architecture HA_CONCURRENTof HALF_ADDER is begin

SUM <= A xor B after 8 ns;
CARRY <= A and B after 4 ns; end
HA_CONCURRENT;

The dataflow model for the HALF_ADDER is described using two concurrent signal assignment
statements (sequential signal assignment statements are described in the next section). In a signal
assignment statement, the symbol <= implies an assignment of a value to a signal.

c. Behavioral Style of Modeling

In contrast to the styles of modeling described earlier, the behavioral style of modeling specifies
the behavior of an entity as a set of statements that are executed sequentially in the specified
order. This set of sequential statements, that are specified inside a process statement, do not
explicitly specify the structure of the entity but merely specifies its functionality. A process
statement is a concurrent statement that can appear within an architecture body. For example,
consider the following behavioral model for the D-flip flop entity.

entity LS_DFF is port (Q: out

BIT; D, CLK: in BIT):
end LS_DFF;
Page
architecture LS_DFF_BEH of LS_DFF is
begin process (D, CLK) begin
if (CLK = '1') then
Q <= D; end if;
end process; end
d. Mixed Style of Modeling

It is possible to mix the three modeling styles that we have seen so far in a single architecture
body. That is, within an architecture body, we could use component instantiation statements (that
represent structure), concurrent signal assignment statements (that represent dataflow), and
process statements (that represent behavior). Here is an example of a mixed style model for a
one-bit full-adder shown in Fig. 2.7.

entity FULL_ADDER is
port (A, B, CIN: in BIT; SUM, COUT: out BIT); end
FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is component

XOR2
port (A, B: in BIT; Z: out BIT);
end component;
signal S1: BIT; begin
X1: XOR2 port map (A, B, S1 ); - structure.
process (A, B, CIN) - behavior.
variable T1, T2, T3: BIT;
begin T1 :=A
and B;
T2 := B and CIN;
T3:=A and CIN;
COUT <= T1 or T2 or T3;
Page
end process;
SUM <= S1 xor CIN; - dataflow. end
FA_M!XED;

The full-adder is represented using one component instantiation statement, one process statement
and one concurrent signal assignment statement. All of these statements are concurrent
statements, and therefore, their order of appearance within the architecture body is not important.
Note that a process statement itself is a concurrent statement; however, statements within a
process statement are always executed sequentially. SI is a signal locally declared within the
architecture body and is used to pass the value from the output of the component XI to the
expression for signal SUM.

3. Model analysis:
Once an entity is described in VHDL, it can be validated using an analyzer and a simulator that
are part of a VHDL system. The first step in the validation process is analysis. The analyzer
takes a file that contains one or more design units (remember that a design unit is an entity
declaration, an architecture body, a configuration declaration, a package declaration or a package
body) and compiles them into an intermediate form. The format of this compiled intermediate
representation is not defined by the language. During compilation, the analyzer validates the
syntax and performs static semantic checks. The generated intermediate form is stored in a
specific design library, that has been designated as the working library.

4. Simulation:
Once the model description is successfully compiled into one or more design libraries, the next
step in the validation process is simulation. For a hierarchical entity to be simulated, all of its
lowest level components must be described at the behavioral level.

Simulation commences by advancing time to that of the next event. Values that are scheduled to
be assigned to signals at this time are assigned. Each process that has a signal in its sensitivity
list whose value just changed, is executed until it suspends. Simulation stops when a
userspecified time limit is reached.

Structural Modeling
Component Declaration

A component instantiated in a structural description must first be declared using a component

declaration. A component declaration declares the name and the interface of a component. The
interface specifies the mode and the type of ports. The syntax of a simple form of component
declaration is

component component-name
Page
port ( list-of-interface-ports ) ; end
component;

The component-name may or may not refer to the name of an already ex-isfing entity in a library.
If it does not, it must be explicitly bound to an entity; otherwise, the model cannot be simulated.
This is done using a configuration.

Component Instantiation

A component instantiation statement defines a subcomponent of the entity in which it appears. It

associates the signals in the entity with the ports of that subcomponent. A format of a component
instantiation statement is

component-label: component-name port map ( association-list) ',

The component-label can be any legal identifier and can be considered as the name of the
instance. The component-name must be the name of a component declared earlier using a
component declaration. The association-list associates signals in the entity, called actuals, with
the ports of a component, called locals.

VHDL codes for some digital circuits:

1) DATA FLOW CODING STYLE FULL ADDER

entity fulladder1 is

port(a,b,cin : in std_logic; sum,carry : out std_logic);

end fulladder1;

architecture beh of fulladder1 is

component halfadder is

port(a,b : in std_logic;

sum,carry : out std_logic);

end component;

component orgate is

port(a,b : in std_logic; c : out std_logic);

end component;
Page
signal temp, temp1, temp2 : std_logic;

begin

u1 : halfadder port map

(a=>a,

b=>b,

sum=>temp,

carry=>temp1);

u2 : halfadder port map

(a=>temp,
b=>cin,

sum=>sum,

carry=>temp2);

u3 : orgate port map

(a=>temp2,

b=>temp1,

c=>carry);

end beh;

2) BEHAVIORAL CODING STYLE

HALF ADDER

entity halfadder is

port(a,b : in std_logic; sum,carry : out std_logic);

end halfadder;

architecture beh of halfadder is

begin
Page
 process(a,b)

begin

if a='0' and b='0'then

sum<='0';

carry<='0';

elsif a='0' and b='1'then

sum<='1';

carry<='0';

else

sum<='0';

carry<='1';

end if;

end process;

end beh;

2) STRUCTURAL CODING

STYLE FULLADDER

entity fladder is

port(a,b,cin : in std_logic; sum,carry : out std_logic);

end fladder;

architecture beh of fladder is

component hfadder is

port(a,b : in std_logic; sum,carry : out std_logic);

Page
end component;

component orgate is

port(a,b : in std_logic; q : out std_logic);

end component;

signal temp,temp1,temp2 : std_logic;

begin

u1: hfadder port map(a=>b,b=>b,sum=>temp,carry=>temp1);

u2: hfadder port map(a=>temp,b=>cin,sum=>sum,carry=>temp2);

u3: orgate port map(a=>temp2,b=>temp1,q=>carry);

end beh;

Chapter 4 Tool description: TANNER EDA

Tanner is an EDA (Electronic design automation) tool, which is used to design and produce
electronic systems ranging from printed circuit boards (PCBs) to integrated circuits.

User Interface:

S-Edit’s user interface consists of the Title Bar, Menu Bar, Work Area, Status Bar, & 5 toolbars.

Getting
Started:
Launch S-Edit; double-click on the S-Edit icon.
Page
 Browsing symbols

Designing the circuit using the components browsed

Enter the T-spice mode

Page
Inserting
the
commands

Run simulation

Page
 Generation
-E
of waveform
d
in W it

CONCLUSION
 Learned the various technology, application and scope of VLSI.
 Learned about the applications of VLSI design
 Learned about the hardware implementation of VLSI

References
Books:

VHDL programming by examples

-Douglas L. Perry
Introduction to HDL based VLSI design
-Chandra Shekhar
Websites:

http://www.wikipedia.org/
http://www.tannereda.com/
Page