Basic VLSI Design Concept
Very-large-scale integration (VLSI) is the process of creating an integrated
circuit (IC) by combining thousands of transistors into a single chip. VLSI began in
the 1970s when complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had a limited set of
functions they could perform. An electronic circuit might consist of a CPU, ROM,
RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
5-layer cross-section of chip
The electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration technologies
and system design applications. With the advent of very large scale integration
(VLSI) designs, the number of applications of integrated circuits (ICs) in high-
performance computing, controls, telecommunications, image and video
processing, and consumer electronics has been rising at a very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate
video and cellular communications provide the end-users a marvelous amount of
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Basic VLSI Design Concept
applications, processing power and portability. This trend is expected to grow
rapidly, with very important implications on VLSI design and systems design.
Why VLSI?
Integration improves the design
– Compactness: less area, physically smaller
– Higher speed: lower parasitics (reduced interconnection
length)
– Lower power consumption
– Higher reliability: improved on-chip interconnects
Integration significantly reduces manufacturing cost
VLSI Design Flow
The VLSI IC circuits design flow is shown in the figure below. The various levels of
design are numbered and the blocks show processes in the design flow.
Specifications comes first, they describe abstractly, the functionality, interface,
and the architecture of the digital IC circuit to be designed.
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Behavioral description is then created to analyze the design in terms of
functionality, performance, compliance to given standards, and other
specifications.
Behavioral or Functional Design
– Only behavior and timing without implementation issue
– Specify behavior based on Input + output + timing
– Fast emulation and debugging for the system
RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.
Logic Design
– Control flow, word widths, register allocation, arithmetic operations, and logic
operations
– RTL (Register Transfer Level)
– HDL (Hardware Description Language)
» Verilog – most popular
» VHDL – Europe and Eastern
» Literal + Timing Information
RTL description is then converted to a gate-level netlist using logic synthesis
tools. A gate level netlist is a description of the circuit in terms of gates and
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connections between them, which are made in such a way that they meet the
timing, power and area specifications.
Simulation: The functional behavior of the design (or a parameter such as power)
is determined by applying a set of excitation vectors to a circuit model.
Circuit Design
– Boolean Expression → Circuit Elements (Cells, Macros, Gates, Transistors) +
Interconnection
– Each component has specific timing and power Info.
– Circuit Simulation: Verify the correctness and timing
– Terms – Netlist, Schematic
– Logic Synthesis Tools : RTL → Netlist
Physical Design
– Netlist → Layout (Geometry Representation)
» Design rules of applied fabrication process
– Layout Synthesis Tools
» Automatic conversion (Fully/Partially)
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» Area and performance penalty
– Crucial Challenges – Area/Delay
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Fabrication
– Layout→ Photo-lithographic mask
» One mask for each layer
– Wafer : Silicon crystal are grown & sliced
– Deposition, and diffusion of various materials on the
wafer : each step uses one mask
– Term : Tape Out, 8 inch/20cm, 12 inch/30cm
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Packaging, Testing, and Debugging
– For PCB (Printed Circuit Board) : DIP (Dual In-line
Package), PGA (Pin Grid Array), BGA (Ball Grid
Array), and QFP (Quad Flat Package)
– For MCM (Multi-Chip Modules): no packaged
– Testing
» Before Package –Probe line testing
» After Package –Tester machine applies test patterns.
VLSI Design Styles
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Full Custom Design
Following the partitioning, the transistor level design of the building block is
generated and simulated.
The example shows a 1-bit full-adder schematic and its SPICE simulation results.
The main objective of full custom design is to ensure fine-grained regularity and
modularity.
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Full Custom SRAM
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HDL-Based Design
The design is synthesized and mapped into the target technology. The logic gates
have one-to-one equivalents as standard cells in the target technology.
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Standard Cells Standard Cells
Library Construction:
– To enable automated placement of the cells and routing of inter-cell
connections, each cell layout is designed with a fixed height, so that a
number of cells can be abutted side-by-side to form rows.
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After chip logic design being done by using standard cells from the library
– Place the individual cells into rows
– Interconnect them that meets the design goal in circuit speed, chip area and
power consumption.
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Mask Gate Array
Metal mask design and processing
Chip utilization factor is higher than the FPGA and so is speed.
Number of gates: hundreds of thousands of logic gates
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FPGA Field Programmable Gate Array: FPGA
User programming
Very short turn around time
Price is higher than standard cell and mask gate array.
Number of gates: 25,000 ~ 20,000 gates
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