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Lecture 10
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Sequential Statements
Sequential Statements
• Sequential statements are statements which are analyzed serially one after the other.
• Sequential statements are allowed only inside process and subprograms (function and
procedure)
• The Process statement is the primary concurrent VHDL statement used to describe
sequential behaviour.
Process statement
• The process statement is a concurrent statement , which delineates a part of an
architecture where sequential statements are executed.
• Syntax
[label:] process [(sensitivity list )]
[declarations]
begin
sequential statements
end process;
Process statement
• Process is a concurrent statement in which sequential statements are allowed.
• An architecture can contain multiple processes. Each process is executed concurrently
• The order of execution of statements is the order in which the statements appear in the
process
• The simulator runs a process when any one of the signals in the sensitivity list changes.
For a wait statement, the simulator executes the process after the wait is over.
✓ process(clk , reset) ...
✓ is executed when either ‘clk’ or ‘reset’ changes
• Each Process is activated at least once at the beginning of the process, independent of
the sensitivity list.
• All signal assignments occur at the END PROCESS statement in terms of simulation.
Process Statement
The use of wait statements
Proc2: process
begin
x <= a and b and c;
wait on a, b, c;
end process;
Sequential Statements
BEGIN BEGIN
IF rising_edge(Clock) THEN -- +ve edge clock IF falling_edge(Clock) THEN -- -ve edge clock
Q <= D;
Q <= D;
END IF;
END IF;
END PROCESS;
END PROCESS;
END Behavior;
END Behavior;
The case statement - syntax
case expression is • The case statement selects, for execution one
when choice 1 =>
of a number of alternative sequences of
statements
when choice 3 to 5 => statements .
statements • Corresponds to with select in concurrent
when choice 8 downto 6 =>
statements .
statements
when choice 9 | 13 | 17 => • Case statement does not result in prioritized
statements logic structure unlike the if statement.
when others =>
statements
end case;
The case statement contd.
process(sel, a, b, c, d)
process (count) begin
begin case sel is
case count is when “00” =>
when 0 => dout <= a;
dout <= “00”; when “01” =>
when 1 to 15 => dout <= b;
dout <= “01”; when “10” =>
when 255 downto 16 => dout <= c;
dout <= “10”; when “11” =>
when others => dout <= d;
dout <= “11”; when others =>
end case; null;
end process; end case;
end process;
Multiplexer Example
-- Sequential Assignment -- Concurrent Assignment
process ( control )
begin with control select
control
case control is Out_1 <= in1 when “00”
when “00” => out_1 <= in1; in2 when “01”
when “01” => out_1 <= in2; in1 in3 when “10”
in2 Out_1 in4 when “11”;
when “10” => out_1 <= in3; in3
when “11” => out_1 <= in4; in4
end behavior ;
end case;
end process;
for-loop
[label:] FOR identifier IN range LOOP process (reset)
(sequential statements) begin
END LOOP [label]; if reset = '1' then
for i in 4 downto 0 loop
if i /= 2 then
Note
x<=x*i;
For the for loop the loop index is
incremented end if;
end loop;
end if;
end process;
FSM in VHDL
Moore FSM Coding
17
ENTITY FSM_Parity IS
PORT ( i1, CLK: IN std_logic;
o1: OUT std_logic);
END FSM_Parity; 0 1 1
0 1 1
S1/0 S2/1
18
Mealy FSM Coding
20
entity seqdetb is
1/1
port (clk: in STD_LOGIC;
0/0
din: in STD_LOGIC; 1/0
dout: out STD_LOGIC);
end seqdetb; 0/0 s0 s1 s2 s3
1/0 1/0 0/0
sreg: process(clk)
begin
if rising_edge(clk)then
present_state <= next_state;
end if;
end process;
Mealy FSM Coding
21 C1: process(present_state, din)
begin
case present_state is
1/1
when s0 =>
0/0
if din = '1' then 1/0
end if;
when s1 =>
if din = '1' then
next_state <= s2; dout <= '0';
else
next_state <= s0; dout <= '0';
end if;
Mealy FSM Coding
21
when s2 =>
if din = '0' then
next_state <= s3;
dout <= '0';
1/1
else
0/0 next_state <= s2;
1/0
dout <= '0';
end if;
0/0 s0 s1
1/0
s2
0/0
s3 when s3 =>
1/0
if din = '1' then
0/0
next_state <= s1;
dout <= '1' ;
else
next_state <= s0;
dout <= '0';
end if;
when others =>
null;
end case;
end process;
FSM in VHDL
21
Next-State Logic
Present-State
Process (clock)
Begin
if rising_edge (clock) then
Present_State <= Next_State;
end if;
End process;
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