SCOE Vadgaon Pune

UNIT III
Algorithmic State Machine
Syllabus

ASM & VHDL

 Algorithmic State Machines: Finite State Machines (FSM) and ASM, ASM
charts, notations, construction of ASM chart and realization for sequential
circuits, Examples: Sequence Generator, Types of Counter.

 VHDL: Introduction to HDL, Data Objects & Data Types, Attributes., VHDL-
Library, Design Entity, Architecture, Modeling Styles, Concurrent and
Sequential Statements,

 Design Examples: VHDL for Combinational Circuits-Adder, MUX, VHDL for

Sequential Circuits, Synchronous and Asynchronous Counter.

 2 Bit Comparator (Behavioral Modeling)
3

library IEEE; if a > b then

use IEEE.STD_LOGIC_1164.ALL; G <= '1';
use IEEE.STD_LOGIC_ARITH.ALL; E <= '0';
use IEEE.STD_LOGIC_UNSIGNED.ALL; L <= '0';
elsif a = b then
entity comp_2a is E <= '1';
Port ( a,b : in std_logic_vector(1 downto 0); G <= '0';
G : out std_logic; -- a > b L <= '0';
E : out std_logic; -- a = b elsif a < b then
L : out std_logic); -- a < b L <= '1';
end comp_2a; G <= '0';
E <= '0';
architecture Behavioral of comp_2a is
begin
process (a,b) end if;
begin end process;
end Behavioral;
SCOE, SE E&TC (DLD)
 2 Bit Comparator (Behavioral Modeling)
4

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; if a > b then G <= '1';
use IEEE.STD_LOGIC_ARITH.ALL; else G <= 'Z';
use IEEE.STD_LOGIC_UNSIGNED.ALL; end if;

entity comp_2c is if a = b then E <= '1';

Port ( a, b : in std_logic_vector(1 downto 0); else E <= 'Z';
G : out std_logic; -- a > b end if;
E : out std_logic; -- a = b
L : out std_logic); -- a < b if a < b then L <= '1';
end comp_2c; else L <= 'Z';
end if;
architecture Behavioral of comp_2c is
begin end process;
process (a, b) end Behavioral;
begin
SCOE, SE E&TC (DLD)
 2 Bit Comparator (Dataflow Modeling)
5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; architecture Behavioral of comp_2b is
begin
entity comp_2b is G <= '1' when a > b else 'Z';
Port ( a, b : in std_logic_vector(1 downto 0); E <= '1' when a = b else 'Z';
G : out std_logic; -- a > b L <= '1' when a < b else 'Z';
E : out std_logic; -- a = b end Behavioral;
L : out std_logic); -- a < b
end comp_2b;

SCOE, SE E&TC (DLD)

 D flip – flop (With Preset & Clear Pin)
6

library IEEE;
architecture Behavioral of D_FF is
use IEEE.STD_LOGIC_1164.ALL;
begin
use IEEE.STD_LOGIC_ARITH.ALL;
process (CLK, Preset, Clear)
use IEEE.STD_LOGIC_UNSIGNED.ALL;
begin
if Clear = '1' then
entity D_FF is
Q <= '0';
Port ( D : in std_logic;
elsif Preset = '1' then
CLK : in std_logic;
Q <= '1';
Preset : in std_logic;
elsif clk'event and clk = '1' then
Clear : in std_logic;
Q <= D;
Q : out std_logic);
end if;
end D_FF;
end process;
end Behavioral;

SCOE, SE E&TC (DLD)

 JK flip – flop Using if – else statement
7
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; begin
entity jk_ff1 is
Port ( J : in std_logic;
K : in std_logic;
CLK : in std_logic;
Reset : in std_logic;
Q : out std_logic;
Qbar : out std_logic);
end jk_ff1;
architecture Behavioral of jk_ff1 is
signal state : std_logic;
begin
process (CLK, Reset)
if Reset = '1' then
state <= ‘0';
elsif clk'event and clk = '1' then
if J = '0' and K = '0' then state <= state;
elsif J = '0' and K = '1' then state <= '0';
elsif J = '1' and K = '0' then state <= '1';
elsif J = '1' and K = '1' then state <= not
state;
end if;
end if;
end process;
Q <= state;
Qbar <= not state;
SCOE, SE E&TC (DLD)
end Behavioral;
 JK flip – flop Using Case Statement
8
begin
library IEEE;
process (CLK, Reset)
use IEEE.STD_LOGIC_1164.ALL;
begin
use IEEE.STD_LOGIC_ARITH.ALL;
if Reset = '1' then
use IEEE.STD_LOGIC_UNSIGNED.ALL;
state <= ‘0';
elsif clk'event and clk = '1' then
entity jk_ff is
flip_flop_state <= J&K;
Port ( J : in std_logic;
case flip_flop_state is
K : in std_logic;
when "00" => state <= state;
CLK : in std_logic;
when "01" => state <= '0';
Reset : in std_logic;
when "10" => state <= '1';
Q : out std_logic;
when "11" => state <= not state;
Qbar : out std_logic);
when others => null;
end jk_ff;
end case;
end if;
architecture Behavioral of jk_ff is
end process;
signal state : std_logic;
Q <= state;
signal flip_flop_state :
Qbar <= not state;
std_logic_vector (1 downto 0); SCOE, SE E&TC (DLD)
end Behavioral;
 4-bit Ripple UP/Down Counter
9
architecture Behavioral of updown is
library IEEE; signal value : std_logic_vector (3 downto 0);
use IEEE.STD_LOGIC_1164.ALL; begin
use IEEE.STD_LOGIC_ARITH.ALL; process (clk, clear, mode)
use IEEE.STD_LOGIC_UNSIGNED.ALL; begin
if clear = '1' then -- clear the counter
entity updown is value <= "0000";
Port (clk : in std_logic; elsif clk'event and clk = '1' then
clear :in std_logic; if mode = '0' then
mode : in std_logic; value <= value + 1; --- up counter
q : out std_logic_vector (3 downto 0)); for mode = 0
end updown; else
value <= value - 1; --- down counter
for mode = 1
end if;
end if;
q <= value;
end process; SCOE, SE E&TC (DLD)
end Behavioral;
 4-bit Synchronous Counter
10

library IEEE; architecture Behavioral of sync is

use IEEE.STD_LOGIC_1164.ALL; signal value : std_logic_vector (3 downto 0);
use IEEE.STD_LOGIC_ARITH.ALL; begin
use IEEE.STD_LOGIC_UNSIGNED.ALL; process (CLK) ---Syn Reset
begin
entity sync is if clk'event and clk='1' then
Port ( CLK : in std_logic; if RESET = '1' then
RESET : in std_logic; value <= "0000";
ENABLE : in std_logic; --value <= (others => '0');
COUNT : out std_logic_vector(3 downto 0)); elsif ENABLE = '1' then
end sync; value <= value + 1;
else
null;
end if;
end if;
end process;
COUNT <= value;
end Behavioral; SCOE, SE E&TC (DLD)
Thank You