Experiment No.

3
FLIP FLOP
Course Code: CPE 402 Program: BSCPE
Course Title: Advanced Logic Circuit Date Performed: November 22, 2016
Section: CPE42FB1 Date Submitted: November 29, 2016
Members: Nonat, Paul Vincent Instructor: Engr. Menchie Miranda
De Vera, Jim Paul
Banoog, Davies
Tampoco, Jonaliza
1. Objective(s):
The activity aims to differentiate the other types of Flip Flop
2. Intended Learning Outcomes (ILOs):
The students shall be able to:
2.1 Compare the clock signal of JK ,D Flip Flop, and T Flip Flop
2.2 Identify the Look Up Table (LUT), Input Output Block (IOB), number of
Slices and Propagation delay of each circuit.

3. Discussion:

D flip flop is actually a slight modification of the above explained clocked SR flip-flop.
From the figure you can see that the D input is connected to the S input and the
complement of the D input is connected to the R input. The D input is passed on to the
flip flop when the value of CP is 1. When CP is HIGH, the flip flop moves to the SET
state. If it is 0, the flip flop switches to the CLEAR state.

Figure 3.1 Logic Diagram and Block Diagram of D Flip Flop

J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference
is that the intermediate state is more refined and precise than that of a S-R flip flop.

The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The
letter J stands for SET and the letter K stands for CLEAR.
 Figure 3.2 Logic Diagram and Block Diagram of JK Flip Flop

When both the inputs J and K have a HIGH state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to
Q=1.
4. Resources:

4.1 A personal computer with installed Xilinx Software

4.2 Internet connection (recommended but not required)

5. Procedure:

Creating a New Project

Create a new ISE project which will target the FPGA device on Spartan 6 SP601
Evaluation Board.

5.1.1 In the File> New Project > to open the New Project Wizard.
5.1.2 In the Project Name field type D_Flip Flop.
5.1.3 In the Project menu choose New Source.
5.1.4 Select Source type dialog box select VHDL Module Source
5.1.5 File Name field type Latch.
5.1.6 Verify that the Add to Project checkbox is selected. Click Next
5.1.7 In the Entity Name field type dff and in Architecture Name field type behv .
5.1.8 Double click the Port name field and declare the necessary variables or identifier.

How to Create VHDL Test Bench

Design Simulation
Verifying functionality using Behavioral Simulation
Once the syntax is checked add a VHDL Test Bench file to the file to run simulation.
5.3.1 In the Project menu select New Source
5.3.2 In the New Source Wizard Select VHDL Test Bench for the source type
and enter testbench name for the file.
5.3.3 Click Next.
5.3.4 In associate Source dialog you will be asked to select the source file you
 want to associate with the given test bench file. This dictates which source
file actually runs the simulation on. We run the simulation on the top level
module of the design (file}. Click Next.
5.3.5 In Summary window click Finish to complete the creation.
5.3.6 In the Design panel select Simulation radio button to view the file.
5.3.7 You will see that the Xilinx has already generated lines of code to start the
input definition. Scroll down the test bench to see the code between initial
begin and end blocks.
5.3.8 Save the file by Selecting File Save.
5.3.9 Go to the Process Panel, expand the ISim Simulator and double click
Simulate Behavioral Model.
5.3.10 Repeat the same procedure for Decoder, Multiplexer and Demultiplexer.
5.3.11 Implement the modules to the FPGA Board. (Refer to Experiment 2 for the
procedure).
6. Activity:
6.1 Test the given module D Flip Flop, T Flip Flop, and JK Flip Flop.
6.2 Identify the LUT, IOB and number of slices of each circuit.
6.3 Create the test bench of each Flip Flop according to the given module
6.4 Sketch the RTL Schematic and simulation timing diagram.

D Flip Flop VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BDNT_D_FLIPFLOP is
port( D: in std_logic;
clock: in std_logic;
Q: out std_logic;
Qbar: out std_logic
);
end BDNT_D_FLIPFLOP;

architecture Behavioral of BDNT_D_FLIPFLOP is

begin

process(D, clock)
variable temporary: std_logic;
begin

if (clock='1' and clock'event) then

temporary:= D;
end if;
Q <= temporary;
Qbar <= not temporary;
end process;
end Behavioral;
VHDL Module Screenshot

D Flip Flop Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY DFF_test IS
END DFF_test;

ARCHITECTURE behavior OF DFF_test IS

COMPONENT BDNT_D_FLIPFLOP
PORT(
D : IN std_logic;
clock : IN std_logic;
Q : OUT std_logic;
Qbar : OUT std_logic
);
END COMPONENT;
signal D : std_logic := '0';
signal clock : std_logic := '0';
signal Q : std_logic;
signal Qbar : std_logic;
 constant clock_period : time := 10 ns;

BEGIN

uut: BDNT_D_FLIPFLOP PORT MAP (D,clock,Q,Qbar);

process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;

process
begin
D <='0';
wait for clock_period*0.5;
D <='1';
wait for clock_period*0.5;
D <='1';
wait for clock_period*0.5;
D <='0';
wait for clock_period*0.5;
end process;

END;
VHDL Test Bench Screenshot
Sketch the resulting RTL Schematic of D Flip Flop

Number of Slices: 0
Number of 4 input LUTs : 0
Number of bonded IOBs: 3
Sketch of simulation timing diagram D Flip Flop
JK Flip Flop VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BDNT_JKFLIPFLOP is
port (
J, K: in std_logic;
clock: in std_logic;
Q, Qbar: out std_logic
);
end BDNT_JKFLIPFLOP;
architecture Behavioral of BDNT_JKFLIPFLOP is
begin
process(clock)
variable temporary : std_logic;
begin
if(rising_edge(clock)) then
if(J='0' and K='0') then
temporary := temporary;
elsif(J='1' and K='1') then
temporary := not temporary;
elsif(J='0' and K='1') then
temporary :='0';
 elsif(J='1' and K='0') then
temporary :='1';
end if;
end if;
Q <= temporary;
Qbar <= not temporary;
end process;
end Behavioral;
VHDL Module Screenshot

JK Flip Flop Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY BDNT_JKTest IS
END BDNT_JKTest;
ARCHITECTURE behavior OF BDNT_JKTest IS
COMPONENT BDNT_JKFLIPFLOP
PORT(
J : IN std_logic;
K : IN std_logic;
clock : IN std_logic;
Q : OUT std_logic;
Qbar : OUT std_logic
);
END COMPONENT;
signal J : std_logic := '0';
signal K : std_logic := '0';
signal clock : std_logic := '0';
 signal Q : std_logic;
signal Qbar : std_logic;
constant clock_period : time := 10 ns;
BEGIN
uut: BDNT_JKFLIPFLOP PORT MAP (J,K,clock,Q,Qbar);
process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
process
begin
while clock_period <= 10 ns
loop
J<='0';
k<='1';
wait for clock_period*1;
J<='1';
k<='0';
wait for clock_period*1;
J<='0';
k<='0';
wait for clock_period*1;
J<='1';
k<='1';
wait for clock_period*1;
end loop;
end process;
END;
VHDL Test bench Screenshot
Sketch the resulting RTL Schematic of JK Flip Flop

Number of Slices: 1
Number of 4 input LUTs : 2
Number of bonded IOBs: 5
Sketch of simulation timing diagram D Flip Flop
T Flip Flop VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BDNT_T_FLIPFLOP is
port(
T, clk, rst : in std_logic;
Q : out std_logic;
Qbar : out std_logic
);
end BDNT_T_FLIPFLOP;
architecture Behavioral of BDNT_T_FLIPFLOP is
signal x : std_logic;
begin
process(T,clk)
begin
if rst = '1' then
x <= '0';
elsif rising_edge(clk) then
if T = '1' then
x <= not x;
else
x <= x;
end if;
end if;
Q <= x;
Qbar <= not x;
end process;
end Behavioral;
VHDL Module Screenshot
T Flip Flop Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test2 IS
END test2;

ARCHITECTURE behavior OF test2 IS

COMPONENT BDNT_T_FLIPFLOP
PORT(
T : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
Q : OUT std_logic;
Qbar : OUT std_logic
);
END COMPONENT;
signal T : STD_LOGIC;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal Q : STD_LOGIC;
signal Qbar : STD_LOGIC;
begin

UUT : BDNT_T_FLIPFLOP
port map (T,clk,rst,Q,Qbar);
clk_pro: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;

sti_pro: process
begin
T <= '0';
rst <= '0';
wait for 10 ns;

T <= '0';
rst <= '0';
wait for 10 ns;

T <= '1';
rst <= '0';
wait for 10 ns;

T <= '0';
rst <= '1';
wait for 10 ns;
 end process;
END behavior;

configuration TESTBENCH_FOR_test2 of test2 is

for behavior
for UUT : BDNT_T_FLIPFLOP
use entity work.test2(model);
end for;
end for;
end TESTBENCH_FOR_test2;
VHDL Test bench Screenshot
Sketch the resulting RTL Schematic of T Flip Flop

Number of Slices: 0
Number of 4 input LUTs : 0
Number of bonded IOBs: 3
Sketch of simulation timing diagram of T Flip Flop
Course: CPE 402 Experiment No.: 3
Group No.: 1 Section: CPE42FB1
Group Members: Nonat, Paul Vincent Date Performed: November 22, 2016
De Vera, Jim Paul Date Submitted: November 29, 2016
Banoog, Davies Instructor: Engr. Menchie Miranda
Tampoco, Jonaliza
7. Data and Results:

7. 1 Explain the use of Flip Flops.

Flip-flops or latches are used as data storage elements for multi-valued logic. Flip
flop can be simple or clocked. Simple flip-flops or transparent are commonly
used for storage elements.

7.2 Differentiate each Flip Flop to one another.

Basic types of flip-flops include (a) S-R Flip Flop, (b) Delay or D Flip Flop, (c) J-K
Flip Flop, and T Flip Flop. S-R or set-reset is the basic type of Flip-flops is
designed with the help of two NOR gates and also two NAND gates. D Flip-flops
is a modification of S-R it has two AND gates and TWO NOR gates and an
inverted D input. The behavior of input J and K is the same as the S and R inputs
of the S-R flip-flops. T flip-flops contain two AND gates with three inputs and two
NOR gates.
8. Conclusion:

Flip-flops are the applications of logic gates. It can be used as data storage
elements. There are four basic types of flip-flops. S-R flip-flops is the basic type it
has two inputs the set and reset and has an output of Q and Q'. D flip-flops is a
modification of S-R flip-flops. It has two inputs D and the clock pulse, the D
inverted is directly connected to R input. J-K flip-flops, J Stands for SET and K
stands for clear. This type of flip-flops has the same behavior as the S-R flip-
flops. Lastly, T flip-flops are the same as the J-K type except for both inputs of J-
K is a single input.
9. Assessment (Rubric for Laboratory Performance):