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Resolved functions
Latches & Flip-Flops
SR-Latch
R Q+ Qn+
Q SR =
Q Qn 00 01 11 10
00 11 01 00 10
Q 01 01 01 00 00
S
11 00 00 00 00
10 10 00 00 10
Gated SR-Latch
R
Q
C
Q
S
D-latch
D
Q
C
Q
D q
Clk
Master-Slave Flipflop
D q
Clk
D q
Clk
Edge-triggered Flipflop
Q
Clk
Q
D
Latches /MUXES
Mux:
a 1
process(a,b,sel) q
begin
b
if (sel='1') then 0
q<=a;
else
q<=b; Sel
end if;
end process;
Latches
Latch:
D 1
process(D,clk) q
(a)
begin
if (clk='1') then 0
q<=D;
end if;
end process; Clk
(Sel)
Flip-flop
D 1 1
q
0 0
Clk
D q
Clk
Flip-flop
signal s:bit;
s
s'event =
s'active =
now
s'stable(5 ns) =
activation
s'quiet(5 ns) =
不影响event
s'transaction =
Signal Attributes
signal s:bit;
s'delayed(5 ns) =
s'last_event =
s'last_active =
s'last_value =
异步复位
D-latch with asynchronous reset
Latch:
process(D,reset,clk) D 1
begin
q
if (reset=‘0’) then
q<='0'; 0
elsif (clk='1') then Reset
q<=D;
end if; Clk
end process;
D-latch with synchronous reset
Latch:
process(D,reset,clk)
begin D
1
Reset
if (clk='1') then q
if (reset='0') then
q<='0';
0
else
q<=D;
end if;
Clk
end if;
end process;
D-flipflop with asynchronous reset
D 1 1
q
0 0
Reset
D q
Clk Clk
Clk
Reset
Asynchronous reset
D 1 1
Reset
q
0 0
D q
Clk Clk
Reset
Clk
Synchronous reset
process(clk) -- synthesis might complain that neither d nor
-- reset is listed
begin
if (clk='1') and clk'event then
if (reset='0') then
q<='0';
else
q<= D;
end if;
end if;
end process;
Registers
D(0 to N-1) Q(0 to N-1)
Clk
Structural description
USE work.all;
ENTITY d_register IS
generic( N:integer );
port( D:IN bit_vector(N-1 DOWNTO 0);
clk:IN bit;
Q:OUT bit_vector(N-1 DOWNTO 0));
END d_register;
ARCHITECTURE structure OF d_register IS
COMPONENT dflipflop -- IS is allowed in VHDL’93 Not very efficient!!!
port( D:IN bit;
clk:IN bit;
Q:OUT bit);
END COMPONENT; -- COMPONENT keyword may be skipped in VHDL’93
BEGIN
U0:FOR i IN 0 TO N-1 GENERATE
R0:dflipflop PORT MAP (D(i),clk,Q(i));
END GENERATE ;
END d_register;
Sequential description (RTL-style)
process(a,b,c,y)
begin
a <= b +c; +
p <= a + y;
end;
+
Variable as Wire
... a
end process; b
process(a,b)
variable x,y;
begin
+
... 1
x := a + b; x
y := x + 1;
...
end process; +
... y
Variable as Latch
process(a,b) a
variable x,y,z; b
begin
...
if cond = '1' then +
x := a + b;
end if; cond
y := x + 1;
... Latch (x)
end process;
1
+
y
Edge Expressions and Clocked
Bodies
Edge Expressions There is no explicit
signal'event and signal ='1' concept of clock in VHDL.
signal'event and signal ='0' The synthesis tool has to
infer the clock.
A WAIT or IF statement
Edge Expressions is normally used to make
process (x,y,z); the sequential behavior
begin synchronous.
if x'event and x = '0' then
...
end if;
Register/Latch Inference Rules
Type of Body
En(0 to N-1)
How do we model bus-
D(0 to N-1) wires?
Clk
Bus Resolution in VHDL
• VHDL does not allow multiple concurrent signal assignments to the
same signal
– Multiple sequential signal assignments inside a process are
allowed (last assignment will be kept)
-- this code will generate an error
ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;
USE WORK.my_bus_resolution.ALL;
ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;
Transaction queue
OR
AND
Bus Resolution Functions
• VHDL uses bus resolution functions to resolve the final value of
multiple signal assignments
• The port mode of the interface describes the direction of the data
flow with respect to the component
type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
'U' - Uninitialized
'X' - Forcing Unknown
'0' - Forcing Zero
'1' - Forcing One
'Z' - High Impedance 高阻抗
'W' - Weak Unknown
'L' - Weak Zero
'H' - Weak One
'-' - Don’t Care
std_logic
En
D Q
Clk
Example: I2C (CAN)-bus protocol
1 2 3 4
How accurate is the
VHDL Resolution model?
VDD
VL
VOH N connected Units
VL
VSS
高低电平
Voltage levels
VOH VH
Noise Margin
VOL VL
Ri
~10 Mohms => 'Z'
Ohms→欧姆Ω
Physical representation of std_ulogic
Vres
<0.8V >0.8V,<2.4V >2.4V - TTL
Rres <10% >10%, <90% >90% - CMOS (% of VDD-VSS)
VDD R
VL
VOH V=VOH
V
R=ROH
VL
VSS
Equivalent Two-pole of output stage
VDD R
VH
VOL V=VOL
V
R=ROL
VH
VSS
'0' - Forcing Zero
R
VDD
VH
VH
VOL V
VL V VH
VSS
'0' '1'
V<VL '1'
R~10 Ohms
'H' - Weak High (Open Drain)
R
VDD
VH V
VOH V
VL VL
VSS
VDD
'0'
VH<V 'H'
R~10 kOhms
'Z' - High Impedance
R
VDD
VH
VH
V=?
V=?
VL VL
VSS
'0' '0'
'Z'
V=?
R~10 MOhms (TTL)
10 GOhms (CMOS)
Two-pole equivalent
Vres
R1 R2
V1 V2
Rres = R1||R2
Vres = V1*R2/(R1+R2)+V2*R1/(R1+R2)
Example: 'X' - Forcing Unknown
R
VH
V V
VL
'X' '1'
VL<V<VH '0'
R~10 Ohms
'X' - Forcing Unknown
VDD VDD
VH VL
VOL VOH
VH VL
VSS VSS
'X' - Forcing Unknown
Vres
VDD
R1 R2
VL
V=? V1 V2
VH
VSS
Apply Voltage-division repeatedly until you get final voltage & resistance:
Vres0 = 0 (V), Rres0 = 1 (GOhm)
Vres := Vi *Rres-1/(Ri+Rres-1)+Vres-1*Ri/(Ri+Rres-1)
Rres := Ri*Rres-1/(Ri+Rres-1)
Final check:
if Rres> 1 (MOhm) then return 'Z';
elsif Vres> 0.9*VDD then
if Rres> 1 (kOhm) then return 'H'; else return '1'; end if;
elsif Vres> 0.1*VDD then
if Rres> 1 (kOhm) then return 'W'; else return 'X'; end if;
else
if Rres> 1 (kOhm) then return 'L'; else return '0'; end if;
end if;
Final Result table
Vres
<0.8V >0.8V,<2.4V >2.4V - TTL
Rres <10% >10%, <90% >90% - CMOS (% of VDD-VSS)
Concurrent statements:
-- D-latch
q<=D when clk='1' else q;
-- D-flipflop
q <= D when clk'event and (clk='1') else q;
q <= D when (NOT(clk'STABLE) AND (clk='1') AND
(clk'LAST_VALUE='0')) else q;
Tristate Modeling - Null Transaction
‘X’
VL<V<VH ‘0’ ‘1’
R~10 Ohms
‘0’ - Forcing Zero
R
VDD
VH
VH
VOL V
VL V VH
VSS
‘0’
V<VL ‘1’ ‘1’
R~10 Ohms
‘1’ - Forcing One
R
VDD
VH V
VL
VOH V
VL VL
VSS
‘1’
VH<V ‘0’ ‘0’
R~10 Ohms
‘Z’ - High Impedance
R
VDD
VH
VH
V=?
V=?
VL VL
VSS
‘0’ ‘0’
‘Z’
V=?
R~10 MOhms (TTL)
10 GOhms (CMOS)
‘W’ - Weak Unknown
R
VDD
VH
V V
V=?
VL
VSS
VDD
‘0’
VL<V<VH ‘W’
R~10 kOhms
VSS
‘L’ - Weak Zero (Open Source)
R
VDD
VH
VH
VOL V
VL V
VSS
‘0’
V<VL ‘L’
R~10 kOhms
VSS
‘H’ - Weak High (Open Drain)
R
VDD
VH V
VOH V
VL VL
VSS
VDD
‘0’
VH<V ‘H’
R~10 kOhms