Tutorial 03 Latch FF State Machines 1

Programmable Logic Devices
Tutorial 3
Michal Kubíček
Department of Radio Electronics, FEEC BUT Brno
Vytvořeno za podpory projektu OP VVV Moderní a otevřené studium techniky CZ.02.2.69/0.0/0.0/16_015/0002430.
Tutorial 3
❑ Latch and Flip-Flop in VHDL

❑ Finite State Machines
page 2 kubicek@vutbr.cz
Latch and Flip-Flop in VHDL
Digital system - sequential
Typical example of a simple synchronous sequence

system
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
Registers
Register implementation: Latch or Flip-Flop?

-- state register -- state register
PROCESS (clk, next_state) BEGIN PROCESS (clk) BEGIN
IF clk = '1' THEN
present_state <= next_state;
END IF;
? IF rising_edge(clk) THEN
present_state <= next_state;
END IF;
END PROCESS; END PROCESS;
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
Registers
LATCH
❑ LATCH = level sensitive D-type register
❑ Whenever the CLK input is in active state, signal from the D input is
forwarded to the Q output (including any glitches)
❑ The data on the D input must be stable around falling edge of the CLK
signal so that there is no metastable state.
CLK D Q
D CLK
Registers
LATCH
❑ The main problem: formation of combinatorial loop
The D input is connected to the Q output whenever the clock signal (CLK) is in active state. In the
example below this results in connection a combinatorial loopback. If the duration of active level of CLK
signal is longer, than delay of the loopback, oscillations can be observed (the system effectively forms a
ring oscillator).
A=Q A Y
D Q
B B
CLK
CLK
Y=D Y=!(A∙B)
Registers
LATCH counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF clk = '1' THEN
counter <= counter + 1;
END IF; +1 Latch
END PROCESS; clk
! WARNING:Xst:737 - Found 8-bit

counter 1 2 3 4 5 latch for signal <citac>. Latches
may be generated from incomplete
case or if statements. We do not
clk recommend the use of latches in
FPGA/CPLD designs, as they may lead
counter+1 2 3 4 5 6 to timing problems.
Registers
LATCH counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF clk = '1' THEN
END IF; +1 Latch
END PROCESS; clk
! [Synth 8-327] inferring latch

counter 1 2 3 4 5 for variable 'data_i_reg'
["latch.vhd":25]
clk
counter+1 2 3 4 5 6
Watch out! "Synth 8-327L"

Registers
Combinatorial loop counter
❑ VHDL inference
PROCESS (counter) BEGIN
counter + 1
END PROCESS;
+1
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_cy<0>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<5>.
Registers
Combinatorial loop
Registers
Combinatorial loop
1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis
may not be accurate. The preferred resolution is to modify the design to remove
combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed
by acknowledging the condition and setting the following XDC constraint on any one of
the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'.
One net in the loop is data_out_OBUF[0]. Please evaluate your design. The cells in the
loop are: data_out_OBUF[0]_inst_i_1.
Registers
Combinatorial loop counter
❑ What about simulation?

PROCESS (counter) BEGIN
counter + 1
END PROCESS;
+1
Behavioral Simulation (ISIM)
ERROR: at 100 ns(10000): Iteration limit 10000 is reached. Possible zero delay
oscillation detected where simulation can not advance in time because signals
can not resolve to a stable value in File
"D:/Project/ISE/MPLD/2016/CV_02/S3E_ALU/SOURCES/comb_loop_test.vhd" Line 19.
Please correct this code in order to advance past the current simulation time.
...and if all latches and combinatorial loops have not been removed,
your faith is worthless; you are still in your sins.
Registers
Flip-Flop
❑ D-type edge sensitive register = D-type Flip-Flop
❑ The signal from D input is transferred to the Q output at every active
clock edge (usually rising edge is considered), no glitches can propagate
through Flip-Flop
❑ The input signal (D) must be stable shortly before and shortly after the
active clock edge (setup/hold time requirement)
CLK D Q
D CLK
Registers
Flip-Flop
❑ Effectively eliminates problem of a combinatorial loopback
The D input is "connected" to the Q output only for a very short time. This time is negligible compared to
a typical delay of any loopback path.
A=Q
B A Y
D Q
B
CLK CLK
Y=D
Registers
Flip-Flop counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF rising_edge(clk) THEN
counter <= counter + 1; D Q
END IF; +1
END PROCESS; clk CLK
counter 1 2
clk
counter+1 2 3
Registers
LATCH – why to use them (in ASICs)?

❑ Less transistors needed -> small chip area
❑ Lower power consumption
❑ Using special design techniques it is possible in ASICs to achieve higher
operating frequency (ex. high-end processors).
Reason: In ASICs it is possible to fully control timing of the whole

design (accurate delay adjustment of all the signal paths)
Registers
LATCH – Why not to use them in FPGAs?

❑ Very difficult to fulfil timing requirements as there is no control of path
delay in FPGA; usually results in race conditions.
❑ Usage of LATCH is not forbidden but designer are strongly discouraged

from it. Some companies explicitly ban any LATCH usage in FPGAs.
❑ Possible inference of combinatorial loopback (HDL code error).
❑ In FPGAs there are registers that can be either set to Flip-Flop or LATCH
function. But using this register as a LATCH saves no resources ➔ no
benefit. Many modern FPGAs feature registers with Flip-Flop function only.
Registers
LATCH – FPGA implementation

In FPGAs there are usually
registers that can be either
set to Flip-Flop or LATCH
function. But using this
register as a LATCH saves
no resources ➔ no
benefit. Many modern
FPGAs feature registers
with Flip-Flop function
only.
Registers
VHDL – inadvertent LATCH inference

❑ Inadvertent LATCH inference from incomplete conditional statement.
PROCESS (set_out, x_in) BEGIN

IF set_out = '1' THEN
x_out <= x_in;
END IF; sequential PROCESS
END PROCESS;
! WARNING: Xst:737 - Found 1-bit latch for signal <x_out>. Latches

may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead
to timing problems.
Registers

PROCESS (set_out, x_in) BEGIN

IF set_out = '1' THEN
x_out <= x_in;
END IF; sequential PROCESS
END PROCESS;
! [Synth 8-327] inferring latch for variable 'x_out'

[latch_demo.vhd:25]
Registers
VHDL – removing the LATCH

❑ Use edge-triggered register – Flip-Flop
PROCESS (clk) BEGIN

IF set_out = '1' THEN sequential PROCESS
x_out <= x_in;
END IF;
END IF; NOTE: The condition "IF set_out = '1' THEN" in this
END PROCESS; example code is also incomplete (there is no corresponding
"ELSE"). However, this will not result in LATCH inference as
the condition is written in an edge sensitive process (after
"rising_edge(clk)" condition).
Registers

PROCESS (OpCode,a,b) BEGIN

IF OpCode = "00" THEN y <= a + b; END IF;
IF OpCode = "10" THEN y <= a - b; END IF;
END PROCESS;
combinatorial PROCESS
! WARNING: Xst:737 - Found 8-bit latch for signal <y>.

Latches may be generated from incomplete case or if statements. We
do not recommend the use of latches in FPGA/CPLD designs, as they
may lead to timing problems.
Registers


IF OpCode = "00" THEN y <= a + b; END IF;
IF OpCode = "10" THEN y <= a - b; END IF;
END PROCESS;
! [Synth 8-327] inferring latch for variable 'y'

[latch_demo.vhd:25]
Registers

❑ Complete the conditional statement
IF OpCode = "00" THEN y <= a + b;
ELSE y <= a - b; END IF;
END PROCESS;
Registers


CASE OpCode IS
WHEN "00" => y <= a + b; x <= X"00";
WHEN "10" => y <= a - b; x <= X"FF";
WHEN OTHERS => y <= a * b;
END CASE;
END PROCESS; combinatorial PROCESS
! WARNING: Xst:737 - Found 8-bit latch for signal <x>.

Latches may be generated from incomplete case or if statements. We
do not recommend the use of latches in FPGA/CPLD designs, as they
may lead to timing problems.
Registers


CASE OpCode IS
WHEN "00" => y <= a + b; x <= X"00";
WHEN "10" => y <= a - b; x <= X"FF";
END CASE;
END PROCESS; combinatorial PROCESS
! [Synth 8-327] inferring latch for variable 'x'

[latch_demo.vhd:25]
Registers
❑ Complete the conditional statement

(using default assignment) combinatorial PROCESS

x <= X"00"; -- default assignment
CASE OpCode IS
WHEN "00" => y <= a + b;
WHEN "10" => y <= a - b; x <= X"FF";
END CASE;
END PROCESS;
Finite State Machines (FSM)
Finite State Machines
Finite State Machine (FSM):

❑ Simple system (program, automaton) which can be in exactly one of its states
at any given time (finite number of states)
❑ The FSM performs transition – changes its state according to next state logic
and input signals.
❑ Based on the current state (and inputs) it generates output signals.
S0
S1
S2
Finite State Machine (FSM)

❑ Finite State Machine can be considered to be generalized counter
❑ The other way around: counters are special case of finite state machines
with dominant counting regime (regular transition between neighboring states)
❑ State machines can be both synchronous and asynchronous
❑ Finite state machine is a special case of Turing Machine (its head may only
perform "read" operations, and always has to move from left to right).
Finite State Machine (FSM)

❑ FSM can be implemented not just using digital circuits (as described on
the following slides), but also in a program or even using a mechanical (or
electro-mechanical) systems.
❑ Program implementation of FSM running on a processor is called a
software realization of a FSM.
❑ Software-based FSMs are usually easier to code, understand (readability)
and modify (maintain).
❑ The reaction of a software based FSM is usually slower compared to
hardware based FSM (implemented in FPGA or ASIC)
9:00 Outputs
controlling
home systems
9:01
next
out
state REG logic
logic clk
rst
Time
adjustment 5:30-7:30 22°C windows obscured
7:30-15:00 18°C
17:00-19:00 23°C
19:00-22:00 23°C windows obscured
22:00-5:30 17°C windows obscured
This FSM is perfectly suitable for software
realization as the reaction time is not critical.
State machines in FPGAs: examples
FPGA-based FSM: real use
Video controller
Resolution 1920 x 1050, 60Hz:
The raw memory throughput

requirement: 121M points/s
For 24b color resolution the net data

rate is 346 MB/s
Exact timing of synchronization

signals is necessary.
Ethernet MAC IEEE Std 802.3-2012 Auto-Negotiation state diagram
8b/10b Encoder/Decoder (1G Ethernet)
8b/10b Encoder (1G Ethernet)

Encoder – simple to describe and implement
(LUT or a combinatorial logic)
8b/10b Decoder (1G Ethernet)
10011100101111100011100101100101010111
0101111100 ≠ K28.5
10011100101111100011100101100101010111
0101111100 ≠ K28.5
10011100101111100011100101100101010111
0101111100 = K28.5
10011100101111100011100101100101010111
11110000 10010110
Another applications
❑ DMA controller
❑ Bus arbiters
❑ Encoders and decoders (RS, LDPC, H.264...)
❑ Different levels of standard protocols (Ethernet MAC...)
In general, the driving factor is Response time / control precision:

• 1 ns – 1 us FPGA-based state machine
• 1 us – 1 ms FPGA-based or software based (choice depends on
many factors, need to be thoroughly analyzed)
• > 1 ms software-based state machine (MCU)
Description of FSM functionality
FSM description
Sate diagrams are the most common tools to

capture FSM functionality
❑ State diagram = oriented graph
❑ State = graph knot
❑ Transition = graph edge
In complex FSMs even some states are sometimes

composed of state diagrams (to make the FSM
description more readable).
FSM description
Sate diagrams
FSM description
CAD tool support

❑ There are graphical tools for FSM
creation/editing.
❑ The output of such graphical tools is an HDL
code. As the code is machine-generated it is very
hard to read/edit.
❑ The original graphical tool is required for FSM
editing ➔ problematic portability.
❑ No support in Xilinx Vivado VHDL / Verilog
FSM description
FSM table ➔ can be easily translated to HDL code

pres_st disp_enable cnt_enable cnt_reset S L next_st
1 - Run
Idle 1 0 1 0 1 Idle
0 0 Idle
1 - Stop
Run 1 1 0 0 1 Lap
0 0 Run
1 - Run
Lap 0 1 0 0 1 Lap
0 0 Lap
1 - Lap
Refresh 1 1 0 0 1 Lap
0 0 Lap
1 - Run
Stop 1 0 0 0 1 Idle
0 0 Stop
State register,
state encoding,
VHDL description of FSM
Generic structure of a FSM
pres_state
next_state outputs_i outputs
inputs
next
out
state REG REG
logic clk logic clk
State register
The state register stores information about current FSM state. Its minimum
required size (number of bits) is given N = log2(M), where M is number of
working (valid, intended) states of the FSM.
N = ceil(log2(M))
0 1 2 ... 14 15
pres_state
4b binary counter:
16 states ➔ minimum size of
next_state outputs
the state register is
N = ceil(log2(16)) = 4
+1 REG
clk
State register
The state register stores information about current FSM state. Its minimum
required size (number of bits) is given N = log2(M), where M is number of
working (valid, intended) states of the FSM.
N = ceil(log2(M))
0 1 2 ... 8 9
pres_state
Decimal counter (single decade):

next_state outputs
10 states ➔ minimum size of the state
register is
N = ceil(log2(10)) =
REG = ceil(3.32) = 4 (registers / FF)
clk
State register
In FPGA use always edge triggered D-type register = Flip-Flop
Other technologies:
soucasny_stav
❑ D, DE registers
❑ T, TE registers pristi_stav vystup
❑ J-K...
+1 REG
clk
Without tight timing control it is not possible to use LATCH (combinatorial loopback
may infer).
Why LATCH cannot be used for FSM in FPGA
PROCESS (clk) BEGIN

IF clk = '1' THEN
counter <= counter + 1; counter
END IF;
END PROCESS;
counter + 1
counter 1 2 3 4 5
+1 Latch
clk
clk
counter+1 2 3 4 5 6
Why to use FLIP-FLOP as a state register
PROCESS (clk) BEGIN

counter <= counter + 1; counter
END IF;
END PROCESS;
counter + 1
D Q
counter 1 2
+1
clk CLK
clk
counter+1 2 3
State signal encoding

After the synthesis the state signal is always represented by n-bit vector:
STD_LOGIC_VECTOR(n-1 DOWNTO 0)
Each state is represented by a unique binary value (combination of 1s and 0s)
Minimum number of bits N required for the state signal for M-state FSM is
N = ceil(log2(M))
FSM with 10 states (M=10) requires at least N=4 bit register (vector) for state register.

There are several different variants of state signal encoding. The difference is in
❑ Size (number of bits) required for state register
❑ Complexity of next-state logic and output logic blocks
❑ Maximum operating frequency (different combinatorial path delay)
❑ Different FPGA resource consumption and power consumption
❑ Number of hazards on output signals at transitions between states

Binary Gray Johnson One-Hot
0000 0000 0000000 000000000000000
0001 0001 0000001 000000000000001
0010 0011 0000011 000000000000010
0011 0010 0000111 000000000000100
0100 0110 0001111 000000000001000
0101 0111 0011111 000000000010000
0110 0101 0111111 000000000100000
0111 0100 1111111 000000001000000
1000 1100 1111110 000000010000000
1001 1101 1111100 000000100000000
1010 1111 1111000 000001000000000
1011 1110 1110000 000010000000000
1100 1010 1100000 000100000000000
1101 1011 1000000 001000000000000
1110 1001 0000000 010000000000000
1111 1000 100000000000000
State signal encoding (Xilinx tools)

❑ Auto – the synthesis will select "the best" encoding
❑ One-Hot – only one of N bits in a vector is in log. 1; suitable for medium FSMs
in FPGAs, high speed, low HW requirements
❑ Compact – optimum number of state registers used
❑ Sequential – simple calculation of the next state (without branching)
❑ Gray – suitable for large FSMs and for those with little branching
❑ Johnson – similar to Gray
❑ User – as specified in the HDL code
❑ Speed1 – properties not specified, usually large number of bits than number of
states, should result in high maximum operating frequency
❑ None – the synthesizer will not extract FSMs

Global setting of preferred FSM encoding (for the whole project)
- synthesis properties

Global setting of preferred FSM encoding (for the whole project)
- synthesis properties

Note! Once the FSM is described in HDL using a recommended method, the
synthesis tool is able to recognize it and to extract it.
The extraction means that the synthesis uses an "optimal" method and structure for
the FSM implementation (which is usually advantageous). At the same time the
synthesis choose "the best" encoding, which may be different to encoding
described in the source HDL code!
The synthesis tool can be directed to not to extract particular FSM using directives
and attributes in HDL code (at the FSM that we do not want extract).

Example of Synthesis Report:
...
Found finite state machine <FSM_1> for signal <current_state>.

-----------------------------------------------------------------------
| States | 12 |
| Transitions | 13 |
| Inputs | 1 |
| Outputs | 12 |
| Clock | clk (rising_edge) |
| Clock enable | clk_EN (positive) |
| Reset | rst (positive) |
| Reset type | synchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
...

...
Analyzing FSM <FSM_1> for best encoding.

Optimizing FSM <MPU_SYS_i/UART_i/UART_Basic_Tx_i/current_state/FSM> on signal <current_state[1:12]> with
one-hot encoding.
------------------------
State | Encoding
------------------------
idle | 000000000001
startb | 000000000010
bit0 | 000000000100
bit1 | 000000001000
bit2 | 000000010000
bit3 | 000000100000
bit4 | 000001000000
bit5 | 000010000000
bit6 | 000100000000
bit7 | 001000000000
stopb0 | 010000000000
stopb1 | 100000000000
------------------------
...

Example of implementation results of one particular FSM with different
encoding selected
One-Hot Speed_1 Gray Compact Sequential Johnson
Fm [MHz] 129 162 139 137 138 115

Logic Utilization:
Slice F-F: 66 74 60 60 60 62
4-input LUTs: 63 65 62 63 63 67
Logic Distribution:
Occ. Slices: 60 61 54 54 54 59
User defined explicit state signal encoding
------------------------------------------------------------------
ARCHITECTURE Behavioral OF UART_FSM IS
TYPE t_stav_UART IS (st_idle, st_bit_0, st_bit_1,

st_bit_2, st_bit_3, st_stop_b);
SIGNAL pres_state : t_stav_UART := st_idle_start_b;
ATTRIBUTE ENUM_ENCODING : STRING;

ATTRIBUTE ENUM_ENCODING OF t_stav_UART:
TYPE IS "000 001 010 100 101 111";
------------------------------------------------------------------
BEGIN
...
Binary counter:
FMS-style description
Binary counter
4-bit counter: 2N = 16 states (0 to (2N – 1) = 15)
State diagram (free-running counter)
0 1 2 ... 14 15
BIN
clk
Binary counter described as a FSM

TYPE t_state IS (st_00, st_01, st_02, ... st_15);
SIGNAL pres_st : t_state := st_00;
SIGNAL next_st : t_state;
For state description a custom data type t_state is used. This data type
will be converted to a STD_LOGIC_VECTOR during the synthesis. Number of
bits (length of the vector) will be set according to the selected sate encoding.

TYPE t_state IS (st_00, st_01, st_02, ..., st_15);
SIGNAL pres_st : t_state := st_00; The HDL coding style match the FSM style ➔
SIGNAL next_st : t_state; the synthesis tool will try to extract, optimize
and implement this system as a FSM
BEGIN
PROCESS (clk) BEGIN PROCESS (clk) BEGIN

IF rising_edge(clk) THEN IF rising_edge(clk) THEN
pres_st <= next_st; CASE pres_st IS
END IF; WHEN st_00 => pres_st <= st_01;
END PROCESS; WHEN st_01 => pres_st <= st_02;
...
PROCESS (pres_st) BEGIN WHEN st_15 => pres_st <= st_00;
CASE pres_st IS END CASE;
WHEN st_00 => next_st <= st_01; END IF;
WHEN st_01 => next_st <= st_02; END PROCESS;
pres_state
...
WHEN st_15 => next_st <= st_00;
END CASE; next_state outputs
END PROCESS;
Note that there is no need to use inputs
next
OTHERS case when using enumerated state REG
out
page 68 data type and all choices are covered. logic clk
logic
Output decoder (logic)

PROCESS (pres_st) BEGIN
CASE pres_st IS
WHEN st_00 => out <= "0000";
WHEN st_01 => out <= "0001";
WHEN st_02 => out <= "0010";
WHEN st_03 => out <= "0011";
...
WHEN st_15 => out <= "1111";
END CASE;
END PROCESS;
pres_state
next_state outputs
inputs
next
out
state REG
page 69 kubicek@vutbr.cz logic clk
logic
Using the recommended HDL coding style for binary

counter
The HDL coding style match the counter style
SIGNAL pres_st: INTEGER RANGE 0 TO 15 := 0; ➔ the synthesis tool will try to extract, optimize
and implement this system as a counter.
BEGIN
PROCESS (clk) BEGIN

pres_st <= pres_st + 1;
END IF;
END PROCESS;
out <= STD_LOGIC_VECTOR(TO_UNSINGED(pres_st,4));
pres_state
next_state outputs
inputs
next
out
state REG
logic
4-bit binary counter: synthesis results

HDL description style FSM Counter
Selected state encoding One-hot Speed1 Compact Gray Sequential -
Maximum frequency [MHz] 262 287 375 375 375 375
Flip-Flops 16 20 4 4 4 4
LUTs 57 100 6 6 4 4
Note the same results for FSM with Sequential encoding and the counter style description.
The encoding can be selected directly in the VHDL code (for each state machine independently):
SIGNAL pres_st: INTEGER RANGE 0 TO 15 := 0;

ATTRIBUTE fsm_encoding : STRING;
ATTRIBUTE fsm_encoding OF pres_st : SIGNAL IS "sequential";
-- auto|one-hot|compact|sequential|gray|johnson|speed1|user
4-bit binary counter: synthesis results

HDL description style FSM Counter
Selected state encoding One-hot Speed1 Compact Gray Sequential -
Maximum frequency [MHz] 262 287 375 375 375 375
Flip-Flops 16 20 4 4 4 4
LUTs 57 100 6 6 4 4
In most cases the implemented system (state machine) required a more or less complex output
logic stage which translates current state to the corresponding output number. Only for sequential
encoded FSM and for Counter style this output logic decode was effectively only an interconnection
(no actual logic gates).
pres_state
next_state outputs
inputs
next
out
state REG
logic
Moore and Mealy FSM
Moore Mealy
combinatorial registered state combinatorial registered

outputs outputs outputs outputs outputs
Moore FSM
FSM outputs depend solely on current state
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
Moore FSM with registered outputs
FSM outputs depend solely on current state
pres_state
inputs
next
out
state REG logic
REG
logic clk clk
Mealy FSM
FSM outputs depend both on current state and control inputs.
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
Mealy FSM with registered outputs (pipelined Mealy FSM)
pres_state
inputs
next
out
state REG logic
REG
logic clk clk
FSM with state outputs
pres_state
next_state outputs
inputs
next
state REG
logic clk
How to choose the FSM type?

Strongly depends on requirements
❑ The Moore FSM with state outputs and both Mealy variants are the most common.
❑ Using state outputs enables Moore FSM implementation without output latency.
However, sometimes it is not efficient (too complex FSM).
❑ When immediate (asynchronous) reaction of FSM outputs to an input is required, then
Mealy FSM must be used.
❑ If possible, try to implement several simple FSMs instead of a single large one.
❑ Output of each block (entity) in a design should be registered ➔ try to use only
registered output FSM variants
Than you for your attention !
“Computers are like bikinis. They save people a lot of guesswork.”

(Sam Ewing)

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Programmable Logic Devices

❑ Latch and Flip-Flop in VHDL

Typical example of a simple synchronous sequence

Register implementation: Latch or Flip-Flop?

! WARNING:Xst:737 - Found 8-bit

! [Synth 8-327] inferring latch

Watch out! "Synth 8-327L"

❑ What about simulation?

Behavioral Simulation (ISIM)

LATCH – why to use them (in ASICs)?

Reason: In ASICs it is possible to fully control timing of the whole

LATCH – Why not to use them in FPGAs?

❑ Usage of LATCH is not forbidden but designer are strongly discouraged

❑ Possible inference of combinatorial loopback (HDL code error).

LATCH – FPGA implementation

VHDL – inadvertent LATCH inference

PROCESS (set_out, x_in) BEGIN

! WARNING: Xst:737 - Found 1-bit latch for signal <x_out>. Latches

VHDL – inadvertent LATCH inference

PROCESS (set_out, x_in) BEGIN

! [Synth 8-327] inferring latch for variable 'x_out'

VHDL – removing the LATCH

PROCESS (clk) BEGIN

VHDL – inadvertent LATCH inference

PROCESS (OpCode,a,b) BEGIN

! WARNING: Xst:737 - Found 8-bit latch for signal <y>.

VHDL – inadvertent LATCH inference

PROCESS (OpCode,a,b) BEGIN

! [Synth 8-327] inferring latch for variable 'y'

VHDL – removing the LATCH

VHDL – inadvertent LATCH inference

PROCESS (OpCode,a,b) BEGIN

! WARNING: Xst:737 - Found 8-bit latch for signal <x>.

VHDL – inadvertent LATCH inference

PROCESS (OpCode,a,b) BEGIN

! [Synth 8-327] inferring latch for variable 'x'

VHDL – removing the LATCH

❑ Complete the conditional statement

PROCESS (OpCode,a,b) BEGIN

Finite State Machine (FSM):

Finite State Machine (FSM)

Finite State Machine (FSM)

The raw memory throughput

For 24b color resolution the net data

Exact timing of synchronization

Ethernet MAC IEEE Std 802.3-2012 Auto-Negotiation state diagram

8b/10b Encoder/Decoder (1G Ethernet)

8b/10b Encoder (1G Ethernet)

8b/10b Decoder (1G Ethernet)

In general, the driving factor is Response time / control precision:

Sate diagrams are the most common tools to

❑ State = graph knot

❑ Transition = graph edge

In complex FSMs even some states are sometimes

CAD tool support

FSM table ➔ can be easily translated to HDL code

Generic structure of a FSM

next_state outputs_i outputs

Decimal counter (single decade):

Why LATCH cannot be used for FSM in FPGA

PROCESS (clk) BEGIN

Why to use FLIP-FLOP as a state register

PROCESS (clk) BEGIN