Behavioral Verilog

A Way to Describe
Synchronous Circuits
(It does much more than this –
but we won’t be covering that…)

ECEn 224 © 2003-2011

BYU
 A 4-Bit Register

module reg(q, clk, d); !

parameter WID=4; !
input clk;!
input[WID-1:0] d;!
d 4
D Q q output reg[WID-1:0] q;!
4
!
always @(posedge clk)!
q <= d;!
clk endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 A Loadable Register

module behavLoadableReg (myreg, clk, 


load, din); !
0
parameter WID=4; !
D Q input clk, load;!
myreg input din;!
din 1
output reg myreg;!
!
load always @(posedge clk)!
clk if (load)!
myreg <= din; !
endmodule `!

ECEn 224 A3 Verilog © 2003-2011

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 A Counter

module upCnt (cnt, clk, clr); !

parameter WID=4; !
0
+1 input clk, clr;!
D Q 4
cnt output reg[WID-1:0] cnt;!
4
0000 1
!
always @(posedge clk)!
clr if (clr)!
clk cnt <= 0;!
else!
cnt <= q + 1;!
endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 Current/Next State Values

module upCnt (cnt, clk, clr); !

parameter WID=4; !
0
+1 input clk, clr;!
D Q 4
cnt output reg[WID-1:0] cnt;!
4
0000 1
!
always @(posedge clk)!
clr if (clr)!
clk cnt <= 0;!
else!
cnt <= cnt + 1;!
endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 Another Counter

module upCnt (cnt, clk, clr, inc); !

cnt parameter WID=4; !
4
cnt+1 input clk, clr, inc;!
4 D Q cnt output reg[WID-1:0] cnt;!
0 4 4
!
4
cnt 4 always @(posedge clk)!
2 if (clr && !inc)!
clk cnt <= 0;!
clr inc else if (!clr && inc)!
cnt <= cnt + 1;!
endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 Yet Another Counter

module upCnt (q, clk, clr, inc); !

0 parameter WID=4; !
0
+1 input clk, clr, inc;!
1
D Q 4
q output reg[WID-1:0] q;!
4
1
0000 !
always @(posedge clk)!
inc if (clr)!
clr clk q <= 0;!
else if (inc)!
q <= q + 1;!
endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 A Swapper

module swapper (clk, load, swap, !

a, b, out1, out2); !
0
0 input clk, load, swap;!
1
D Q input a, b;!
a out1 output reg out1, out2;!
1
!
swap
always @(posedge clk)!
load clk if (load)!
begin!
out1 <= a;!
out2 <= b;!
end!
0
0 else if (swap)!
1
D Q begin!
b out2 out1 <= out2;!
1
out2 <= out1;!
end!
swap
load clk endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 A Swapper

module swapper (clk, load, swap, !

a, b, out1, out2); !
0
0 input clk, load, swap;!
1
D Q input a, b;!
a out1 output reg out1, out2;!
1
!
swap
always @(posedge clk)!
load clk if (load)!
begin!
out1 <= a;!
out2 <= b;!
end!
0
0 else if (swap)!
1
D Q begin!
b out2 out1 <= out2;!
1
out2 <= out1;!
end!
swap
load clk endmodule !

ECEn 224 A3 Verilog © 2003-2011

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 Multiple Assignments to a Signal

•  When you assign

twice…
module multiAssign (clk, clr, cnt);
–  Last one takes effect input clk, clr;!

on the signal value

output reg[3:0] cnt;!
!
always @(posedge clk)!
begin!
cnt <= 4'b0000; !
if (!clr)!
0 cnt <= cnt+1; !
+1
D Q 4
cnt end!
4 endmodule !
0000 1

clr
clk

ECEn 224 A3 Verilog © 2003-2011

Page 10 BYU
 A Shift Register

module delay4 (clk, 


Q3 Q2 Q1 Q0 SerIn, Q); !
input clk, SerIn;!
output reg[3:0] Q;!
SerIn D Q D Q D Q D Q !
always @(posedge clk)!
Q <= {SerIn, Q[3:1]};!
endmodule!

CLK CLK CLK CLK

ECEn 224 A3 Verilog © 2003-2011

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 Another Shift Register

module delay4 (clk, shift, 


SerIn, Q); !
input clk, shift, SerIn;!
output reg Q;

a b
SerIn D Q D Q D Q Q reg a, b;!
!
always @(posedge clk)!
begin!
a <= SerIn;!
CLK CLK CLK b <= a;!
Q <= b;!
end!
endmodule!

ECEn 224 A3 Verilog © 2003-2011

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 Yet Another Shift Register

module delay4 (clk, shift, 


SerIn, Q); !
input clk, shift, SerIn;!
output reg Q;

a b
SerIn D Q D Q D Q Q reg a, b;!
!
always @(posedge clk)!
begin!
Q <= b;!
CLK CLK CLK b <= a;!
a <= SerIn;!
end!
endmodule!

Order of assignments DOES NOT MATTER…

ECEn 224 A3 Verilog © 2003-2011

Page 13 BYU
 A Register File

module regFile (clk, regWE, Addr, 


DataIn, DataOut);!
input clk, regWE;!
Reg0 input[2:0] Addr;!
n
Register write signals

Reg1 input[15:0] DataIn;!

n
Reg2 output[15:0] DataOut;!
n 8:1 MUX !
Write Reg3
n reg [15:0] registers [7:0]; !
Decoder Reg4 DataOut
n n=16 !
Reg5 // The synchronous write logic!
n
Reg6 always @(posedge clk)!
n
Reg7 if (regWE)!
n registers[Addr] <= DataIn;!
m=3 n=16 !
regWE DataIn clk // The asynchronous read logic!
Addr assign DataOut = registers[Addr];!
!
endmodule !

ECEn 224 A3 Verilog © 2003-2011

Page 14 BYU
 An FSM
module fsm (clk, reset, Xin, Z);!
To be studied after you learn FSM design input clk, reset, Xin;!
output Z;!
reg[1:0] state;!
Xin !
parameter s0 = 2'b00; !
parameter s1 = 2'b01;!
parameter s2 = 2'b10; !
parameter s3 = 2'b11;!
reset !
S0 always @(posedge clk)!
begin!
Xin if (reset)!
state <= s0;!
else !
case (state)!
S3 Z S1 Xin
s0: if (!Xin) state <= s1;!
s1: if (Xin) state <= s2;!
s2: if (Xin) state <= s1;!
else state <= s3;!
endcase!
Xin
Xin end!
assign Z = state==s3 ? 1'b1 : 1'b0;!
S2 Xin !
endmodule !

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 A Car Wash FSM
To be studied after you learn FSM design module carWash (clk, reset, token, tdone, clrt, spray); !
input clk, reset, token, tdone;!
output reg clrt, spray;!
token reg[1:0] state;!
!
parameter sIdle = 2'b00;!
parameter sToken = 2'b01; !
reset parameter sSpray = 2'b10; !
sIdle !
always @(posedge clk)!
token begin!
if (reset)!
state <= sIdle;!
else !
tdone sToken clrt case (state)!
sIdle: if (token) state <= sToken;!
sToken: state <= sSpray;!
sSpray: if (tdone) state <= sIdle;!
endcase!
end!
spray sSpray !
always @(state)!
begin!
clrt = 1'b0;!
spray = 1'b0;!
case (state)!
tdone sToken: clrt = 1'b1;!
sSpray: spray = 1'b1;!
endcase!
end !
endmodule !
A3 Verilog © 2003-2011
Page 16 BYU
 Finishing Up

•  You should always know what circuitry will

result from a piece of Verilog code
–  Otherwise => recipe for disaster !!!!!

•  Always check your synthesizer documentation

–  Will tell you how to code for synthesis
–  Will let you take advantage of technology-
specific features

ECEn 224 A3 Verilog © 2003-2011

Page 17 BYU