Verilog HDL

Universal Shift Register

 Introduction to Verilog HDL
• Verilog is a hardware description language (HDL) that is
used to model electronic systems.
• Verilog can describe a digital system at different levels of
abstraction, such as behavioural, register-transfer, and gate
level.
• Verilog is based on C language and supports many features
such as functions, tasks, parameters, operators, and data
types.
• Verilog is widely used in the design and verification of digital
circuits, especially at the register-transfer level.
• Verilog allows the creation of testbenches
to simulate and verify the functionality of a design.
Introduction to Universal Shift Register

 The Universal Shift Register is a digital

circuit that can shift data both left and right.

 It can also perform parallel loading of data.

 The shift register is a vital component in

many applications, including data
communication and storage systems.

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Basic Operation of Universal Shift Register

 The Universal Shift Register consists of a

set of flip-flops connected in series.

 The shift register has two modes of

operation: serial and parallel.

 In the serial mode, data is shifted in or out

one bit at a time.

 In the parallel mode, data is loaded all flip-

flops of a register at one time.

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Serial and Parallel Loading

 In serial loading, data is shifted in or out one

bit at a time.

 In parallel loading, all bits are loaded

simultaneously.

 The loading mode is controlled by the

shift/load control signal.

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Verilog Code for Universal Shift Register
Here is an example of Verilog code for a universal
shift register:
module usr(dataout,clock,reset,mode,datain);
output reg[3:0]dataout;
input clock,reset;
input [1:0]mode;
input [3:0]datain;
always@(posedge clock)
begin
if(reset)
dataout<=0;
else
begin
case(mode)
2'b00:dataout<=dataout;
2'b01:dataout<={datain[0],datain[3:1]};
2'b10:dataout<={datain[2:0],datain[3]};
2'b11:dataout<=datain;
endcase
end
end
endmodule

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Verilog Code for Universal Shift Register
Here is an testbench code for a universal shift register:
module usr_testbench();
reg [3:0]datain;
reg clock,reset;
reg [1:0]mode;
wire [3:0]dataout;
usr m1(dataout,clock,reset,mode,datain);
initial begin
clock=0;
repeat(100)
#20 clock=~clock;
end
initial begin
datain=4'b1010; mode=2'b00;reset=1’b0;
#20;
datain=4'b1010;mode=2'b01;reset=1'b0;
#20;
datain=4'b1010;mode=2'b10;reset=1'b0;
#20;
datain=4'b1010;mode=2'b11;reset=1'b0;
#20;
$finish();
end
endmodule

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Applications of Universal Shift Register

 Universal shift registers are commonly used

in serial data communication systems.

 They are also used in storage devices like

shift registers and memory units.

 The flexibility of universal shift registers

makes them suitable for various
applications.

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Summary and Conclusion

 The universal shift register is a versatile

digital circuit that can shift data in both
directions and perform parallel loading.

 Verilog code provides a convenient way to

implement a universal shift register in
hardware.

 Understanding the operation and

applications of the universal shift register is
essential in digital circuit design.

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CN- Flipflop (Change -No Change Flip
Flop) using DFF and 2:1 Mux
Introduction to CN-FLIPFLOP
 In C-N (Change – No change) flip-flop, there
won’t be any change in output as long as N is 0,
irrespective of C.

 If N=1, then if C=0 output will change to 0 else if

C=1 output will be the compliment of previous
output.

 Design C-N flip-flop using D flip flop and

minimum number of 2 x 1 multiplexer.

 The characteristic table and design of the above

flip-flop is shown

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Verilog Code for CN-FLIPFLOP
Here is an example of Verilog code for a cn-flipflop:

2*1 mux code:

module mux21(a,b,s,y);
input a,b,s;
output reg y;
always @(a or b or s)
begin
case(s)
0:y=a;
1:y=b;
default:y=1'b0;
endcase
end
endmodule

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Verilog Code for CN-FLIPFLOP
Here is an example of Verilog code for a cn-flipflop:

*D flipflop code:

module dff(d,clk,reset,q);
input d,clk,reset;
output reg q;
always@(posedge clk)
begin
if(reset)
q=0;
else
q=d;
end
endmodule

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Verilog Code for CN-FLIPFLOP

Here is an example of Verilog code for a cn-flipflop:

module cn_flipflop(c,n,clk,q,qbar);
input c,n,clk;
output q,qbar;
wire cn,n_bar,d_wire;
mux21 mux1(1'b0,c,n,cn);
mux21 mux2(1'b1,1'b0,n,n_bar);
mux21 mux13(cn,n_bar,q,d_wire);
dff dff1(.d(d_wire),.clk(clk),.reset(),.q(q));
assign qbar=~q;
endmodule

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Verilog Code for CN-FLIPFLOP
Here is an testbench code for a CN-flipflop:

module cn_flipflop_testbench();
reg c,n,clk;
wire q,qbar;
cn_flipflop m1(c,n,clk,q,qbar);
initial begin
clk=0;
repeat(100)
#20 clk=~clk;
end
initial begin
c=0;n=0;#20;
c=0;n=1;#20;
c=1;n=0;#20;
c=1;n=1;#20;
end
endmodule

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INTRODUCTION TO A FREQUENCY
DIVIDER BY USING AN ODD
NUMBER
FREQUENCY DIVIDER BY ODD NUMBER
• Frequency or clock dividers are among the most common circuits
used in digital systems.
• Somehow dividing the frequency with an odd number is not that
easy.
• Designing an frequency divider by even number is easy
• A simple odd number frequency divider with 50% duty cycle is
presented. The odd number frequency divider consists of a general odd
number counter and the proposed duty cycle trimming circuit. The duty
cycle trimming circuit can output 50% duty cycle with only additional
six transistors.
circuit diagram of frequency divider
Verilog code
module clk_div3(clk,reset, clk_out);

input clk;
input reset;
output clk_out;

reg [1:0] pos_count, neg_count;

wire [1:0] r_nxt;

always @(posedge clk)

if (reset)
pos_count <=0;
else if (pos_count ==2) pos_count <= 0;
else pos_count<= pos_count +1;

always @(negedge clk)

if (reset)
neg_count <=0;
else if (neg_count ==2) neg_count <= 0;
else neg_count<= neg_count +1;

assign clk_out = ((pos_count == 2) | (neg_count == 2));

endmodule
Testbench for frequency divider
module clkdiv3_tb;
reg clk,reset;
wire clk_out;

clk_div3 t1(clk,reset,clk_out);
initial
clk= 1'b0;
always
#5 clk=~clk;
initial
begin
#5 reset=1'b1;
#10 reset=1'b0;
#100 $finish;
end

initial
$monitor("clk=%b,reset=%b,clk_out=%b",clk,reset,clk_out);

initial
begin
$dumpfile("clkdiv3_tb.vcd");
$dumpvars(0,clkdiv3_tb);
end
endmodule
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