PSG COLLEGE OF TECHNOLOGY

COIMBATORE – 641004

DEPARTMENT OF ELECTRICAL AND ELECTRONICS

ENGINEERING
DIGITAL ELECTRONICS - POSTLAB REPORT

SUBMITTED BY:
KUMBESH BABU B(22E130)
MADHUMITHA K M (22E131)
MEHALAN M(22E132)
MOHAMMED AATHISH N Y (22E133)
MONISH KUMAR S (22E134) SUBMITTED TO:
NANDINI S (22E135) DR.A.NATARAJAN,
NIRAIMATHI T(22E136) PROFESSOR,
NISHANTHINI C(22E137) DEPARTMENT OF EEE

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 TOPIC PAGE NO
SNO
1 AIM 3

2 APPARATUS REQUIRED 3

3 THEORY 3-4

4 VERILOG CODE 4-5

5 OUTPUT 6

6 PRELAB QUESTIONS 7-9

7 POSTLAB QUESTION 9-14

8 RESULT 14

TABLE OF CONTENT

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DESIGN AND SIMULATION OF SIMPLE SEQUENTIAL CIRCUIT USING
VERILOG

AIM
To design and simulation of simple sequential circuits (up down
counter) – 4 bit.
APPARATUS REQUIRED
Vivado 16.2
THEORY
Counter
A Counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in
relationship to a clock signal.
Counters are used in digital electronics for counting purpose, they
can count specific event happening in the circuit.
For example, in UP counter a counter increases count for every rising
edge of clock. Not only counting, a counter can follow the certain sequence
based on our design like any random sequence 0,1,3,2….
They can also be designed with the help of flip flops. They are used
as frequency dividers where the frequency of given pulse waveform is
divided.
Counters are sequential circuit that count the number of pulses can
be either in binary code or BCD form.
The main properties of a counter are timing, sequencing, and
counting.
Counters are broadly divided into two categories
 Asynchronous counter
 Synchronous counter

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4 bit up/down counter
The up/Down counter is also known as the bidirectional counter
which is used to count in any direction based on the condition of the input
control pin. These are used in different applications to count up from zero
to provide a change within the output condition on attaining a fixed value &
others count down from a fixed value to zero to give an output condition
change. There are some types of counters like TTL 74LS190 & 75LS191
which can function in both up & down count mode based on the condition
of an input pin of up/down count mode.

VERILOG CODE
module upordown_counter(
Clk,
reset,
UpOrDown, //high for UP counter and low for Down counter
Count

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 );
//input ports and their sizes
input Clk,reset,UpOrDown;
//output ports and their size
output [3 : 0] Count;
//Internal variables
reg [3 : 0] Count = 0;
always @(posedge(Clk) or posedge(reset))
begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 1) //Up mode selected
if(Count == 15)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 15;
else
Count <= Count - 1; //Decrement counter
end
endmodule

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OUTPUT:
Down counter:

UP COUNTER:

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PRE LAB QUESTIONS

1. Define sequential circuit.

Sequential circuits are digital circuits that store and use the previous state
information to determine their next state. Unlike combinational circuits,
which only depend on the current input values to produce outputs,
sequential circuits depend on both the current inputs and the previous state
stored in memory elements.

2. Difference between synchronous and asynchronous sequential

circuits.

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3.What are the different types of flip flop?

The flip-flops are of the following types:

1. S-R Flip Flop

2. J-K Flip Flop

3. T Flip Flop

4. D Flip Flop

5.J-K master slave

4. Mention any two differences between edge triggering and level

triggering

Edge Triggering Level Triggering

Edge triggering is based on Level triggering is based

detecting a sharp edge on recognizing a specified signal
in the input signal. level.

Level triggering is frequently

Edge triggering is frequently
used in synchronous circuits , such
as counters and flip-flops.
employed in applications that call
for continuous monitoring of an
input signal,
such as data acquisition and
control systems.

Edge triggering is particularly helpful

Level triggering lacks the ability to
in applications that need precise
regulate precise timing.
timing.

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 When edge triggering is used, the
output signal is activated when the
In level triggering, the output
trigger edge is detected and
signal will remain in the triggered
changes to the opposing state. As
condition.
long as the input signal is at or
above the trigger level.

5.Draw the state table and excitation table of T flip flop

State Table Excitation Table

POST LAB

1.Difference between Blocking and non Blocking statement.

BLOCKING STATEMENT NON BLOCKING

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Represented using “=” operator sign
between LHS & RHS
Blocking assignments used to
represent Combinational logic
Blocking assignments can be used in
procedural assignments like initial,
always and continuous assignments to
nets like assign statements
STATEMENT
Represented using “<=” operator sign
between LHS & RHS
Non Blocking assignments are used
to represent Sequential logic
Non Blocking assignment can be
used in procedural assignment like
Initial, always and continuous
assignments to nets like assign
statement is not permitted

2.Write HDL Program for d flip flops with reset.

module d_ff_with_reset (

Input wire clk, // Clock input

Input wire reset, // Reset input

Input wire d, // Data input

Output reg q // Output

);

always @(posedge clk or posedge reset)

begin

If (reset)

q<= 1’b0; // Reset the output to 0 when reset is asserted

else

q<= d; // Update the output with the input data when clocked

end

endmodule

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This code defines a D flip-flop with a reset input. The flip-flop’s output ‘q’
changes according to the input ‘d’ on every rising edge of the clock (clk).
When the reset signal is asserted (i.e., goes high), the output ‘q’ is reset to
0, regardless of the clock state.

3.What is logic synthesis in HDL?

Logic synthesis in HDL (Hardware Description Language) is the process of

translating a high-level hardware description written in a language like
Verilog or VHDL into a netlist of logic gates or other hardware components.

1.Parsing: The HDL code is parsed to understand the structure and

behavior of the described hardware.

2.Optimization: The synthesis tool applies various optimization techniques

to improve the design’s performance, area, and power consumption. This
includes simplifying logic expressions, optimizing for timing constraints, and
reducing resource usage.

3.Mapping to Technology Library: The synthesized design is mapped to

the target technology library, which contains information about the available
logic gates, flip-flops, and other components available in the specific
hardware technology (like ASIC or FPGA).

4.Technology Mapping: The logic components in the netlist are mapped

to their equivalents in the target technology library. For example, logical
AND gates in the netlist might be mapped to physical NAND gates in an
FPGA or ASIC.

5.Timing Analysis: Timing analysis is performed to ensure that the design

meets the required timing constraints, such as clock frequency and
setup/hold times.

6.Verification: The synthesized design is verified to ensure that it behaves

correctly and meets the design specifications.

4.What is timing verification?

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  Timing verification is the process of ensuring that a digital design
meets specific timing requirements or constraints.
 In digital systems, timing is critical because signals must propagate
through various logic elements within specified time limits to ensure
correct operation.
 Timing verification involves analyzing and verifying that the design
meets these timing requirements.
Key aspects of timing verification include:

1.Setup Time and Hold Time: Ensuring that inputs to flip-flops meet
setup and hold time requirements, meaning the inputs must be stable for
a certain time period before and after the clock edge.

2.Clock Frequency: Verifying that the design can operate at the desired
clock frequency without violating timing constraints, such as maximum
clock-to-output delay.

3.Propagation Delay: Analyzing the propagation delay of signals

through combinational logic to ensure that the design meets timing
requirements.

4.Clock Skew: Managing and verifying the skew (variation in arrival

times) of clock signals to prevent timing violations.

5.Data Path Timing: Verifying timing constraints for critical paths in the
data path, ensuring that data can be processed within the required time.

6.Synchronous and Asynchronous Timing: Analyzing timing

requirements for both synchronous and asynchronous components of
the design.

5.Write HDL code for 4 bit ripple counter using t flip flop assume it
has propagation delay of 1 Unit time.
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module ripple_counter (

Input wire clk, // Clock input

Input wire reset, // Reset input

Output reg [3:0] q // Output

);

reg [3:0] next_q;

// T flip-flops with propagation delay

always @(posedge clk)

begin

If (reset)

next_q <= 4’b0000; // Reset the counter

else

next_q <= {next_q[2:0], next_q[3] ^ next_q[0]}; // T flip-flop with toggle

input

end

always @(posedge clk)

begin

#1; // Propagation delay of one unit time

q <= next_q;

end

endmodule

This code implements a 4-bit ripple counter using T flip-flops. The counter
increments on every rising edge of the clock (clk).

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The toggle input of each T flip-flop is connected to the output of the
previous flip-flop, creating a ripple effect. The reset input resets the counter
to zero when asserted

RESULT

Thus the simple sequential circuit (up/down counter) is designed and

implemented using Verilog.

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