Lab 2

GVHD: Tạ Trí Đức

MSSV: 21522612
Name: Bùi Văn Thi

I.Theory

1. Synchronous Counter

- Synchronous counters are sometimes called parallel counters because the clock is sent to all flip-
flops simultaneously. Synchronous counters, built with D-type switches or flip-flops, can perform
faster than their asynchronous counterparts.
- The term “parallel counter” describes these devices. A synchronous counter consists of a series
of flip-flops, each independently linked to an external clock in a cascade connection.
- As a result, when the shared clock signal is applied, the state of all flip-flops changes
simultaneously. Therefore, there is no propagation delay with a synchronous counter because
there is no ripple effect. Synchronous counters use logic gates to regulate the counting process.
This simplifies the use of a single clock input to clock all counter flip-flops.

2.Register File

- In the field of digital electronics and knowledge related to computer microprocessors and
computer architecture, "register file" is an important component in the CPU (Central Processing
Unit) or microprocessor. Register file (roughly translated as register or recorder) is a set of small
registers located in the CPU. Each register is capable of storing a certain value or part of data.
Registers in register files are often used to store intermediate data, intermediate results of
calculations, memory addresses, or other important values during program execution.
- Register files are often used to quickly provide data for microprocessor calculations, helping to
optimize computer performance and speed. Each register in the register file has a unique
address to access it. Calculations and computer instructions will use these addresses to read or
write data to the register file. Registers in the register file are often numbered for easy access
and management.
- Register files are an important part of the microprocessor, especially in performing calculations
and retrieving data from memory. It provides a fast and efficient way to store and access
intermediate values necessary for executing computer instructions.
II.Practice

1. Synchronous Counter

Request: Use behavioral model in verilog to describe process in the image:

1.1 Code:

Explain: This Verilog code defines a 3-bit synchronous counter module named Counter_Syn. Let's break
down the code step by step and explain its functionality
1.Module Declaration

module Counter_Syn (Load, CLK, Load_en, Clear, Out);

This line declares a Verilog module named Counter_Syn with four input ports (Load, CLK, Load_en, and
Clear) and one output port (Out).

 Load is a 3-bit input that can be used to set the initial value of the counter.
 CLK is the clock signal used to synchronize the counter's operations.
 Load_en is an input used to enable the loading of the Load value into the counter.
 Clear is an input used to clear the counter.
 Out is a 3-bit output representing the current value of the counter.

2. Internal Registers:

input CLK, Load_en, Clear;

input [2:0] Load;

output reg [2:0] Out;

reg [2:0] A;

 CLK, Load_en, and Clear are declared as input signals.

 Load is a 3-bit input signal.
 Out is declared as a 3-bit output register.
 A is a 3-bit register used to store the current value of the counter.

3. Always Block:

always @(posedge CLK or negedge Clear or negedge Load_En)

This is a synchronous always block that triggers on the positive edge of the clock signal (CLK). This means
the code inside this block will execute whenever there's a rising edge of the clock signal. And two input
asynchronous Clear and Load_En.

4.Counter Logic:

Inside the always block, the following logic is implemented:

 if (!Clear) checks if the Clear signal is active (logical 0). If it is, the Out signal is set to 0, effectively
clearing the counter.

 else if (!Load_en) checks if the Load_en signal is active (logical 0). If it is, the Out signal is set to
the value of Load. This allows the counter to be loaded with a specific value when Load_en is
low.
 else block: If neither Clear nor Load_en is active, this block executes. It updates the counter
value based on the current value of A.
o The case statement is used to determine the new value of Out based on the current
value of A. The possible cases are listed, and depending on the value of A, a new value
for Out is assigned. Here's what each part of this case statement does:
  If A is 000, Out is set to 110.
 If A is 110, Out is set to 100.
 If A is 100, Out is set to 111.
 If A is 111, Out is set to 011.
 If A is 011, Out is set to 000.
o The default case sets Out to 0 if none of the specified cases match.

5. End of always Block:

This marks the end of the always block.

In summary, this Verilog code defines a 3-bit synchronous counter that can be loaded with an initial
value, cleared, or incremented based on a clock signal (CLK) and control signals (Load_en and Clear). The
counter follows a specific sequence of values defined by the case statement when it's not being cleared
or loaded.

1.2 RTL_Viewer

Explain: Because it is a 3-bit synchronous counter, it requires 3 flip-flops and necessary circuit
combinations to be able to count according to a certain cycle. Here we count according to the cycle (0 ->
6 -> 4 -> 7 -> 3 -> 0) or (5 -> 2 -> 7 -> 3 -> 0 -> 6 -> 4 -> 7 - > 3 -> 0) or (1 -> 6 -> 4 ->7 -> 3 ->0). And the
CLK signal is always activated at the same time.
1.3 Waveform

Explain:

- 0ps -> 200ns: There is no Clear signal and Load_En is turned on so the counter will count in a
cycle from (0 -> 6 -> 4 -> 7 -> 3 -> 0)
- 200ns – 520ns: Load_En is enabled asynchronously (200ns – 240ns) and loads the Load value of
7 into the counter so the counter will count from (7 -> 3 -> 0 -> 6 -> 4 -> 7 - > 3 -> 0 -> 6)
- 520ns – 740 ns: Clear is enabled asynchronously (520ns – 560ns) so the counter will count from
(0 -> 6 -> 4 -> 7 -> 3 -> 0)

Explain:

Consider the sensitivity of the circuit by turning on the Load_En value and then loading the value 2, then
loading the value 3, the circuit continues to load 3 => when Load_En is turned on and after it is turned
off, it is not is turned off completely but will be gradually turned off as follows

2. Register_File 32x32
Request: Use Verilog to design a set of 32 register, each register is 4 bytes.

Signal: ReadAdress[4:0], ReadAddress2[4:0], WriteAddress[4:0], WriteData[31:0], ReadData1[31:0],

ReadData2[31:0], ReadWriteEn, CLK.

2.1 Code:

Explain: This Verilog code defines a 32-bit register file module with two read ports and one write port. It
is designed to store and retrieve data using specified addresses. Let's break down the code step by step

1.Module Declaration:

module Register_File_32bit(CLK, ReadAdress1, ReadAdress2, WriteAdress, WriteData, ReadData1,

ReadData2, RW_En);

- The module is named “Register_File_32bit”

- It has several input and output ports, including CLK (clock signal), ReadAdress1, ReadAdress2,
WriteAdress, WriteData, ReadData1, ReadData2, and RW_En (read/write enable signal)

2.Port Descriptions:

- CLK: This input signal represents the clock signal for the module.
- ReadAdress1 and ReadAdress2: These 5-bit input signals are used to specify the addresses for
the two read ports. Each port can read a 32-bit value from the register file.
- WriteAdress: This 5-bit input signal is used to specify the address for the write port, where data
is written into the register file.
- WriteData: This 32-bit input signal is the data that is written to the register file.
- ReadData1 and ReadData2: These 32-bit output signals represent the data read from the register
file by the two read ports.
- RW_En: This input signal controls the read/write operation. When RW_En is high (1), it indicates
a write operation, and when low (0), it indicates a read operation.

3.Internal Data Structure:

reg [31:0] regis [31:0];

- The code defines an internal 32-bit array called regis to represent the register file. It stores the
data at various addresses.

4.Always Block:

always @(posedge CLK) begin

- Inside the always block, there are two branches based on the value of RW_En, which controls
the operation.
a. Write Operation (When RW_En is 1):
- When RW_En is high (indicating a write operation), the code updates the value at the specified
WriteAdress with the data present on the WriteData input. This is achieved by assigning
WriteData to regis[WriteAdress].
- The ReadData1 and ReadData2 outputs are set to 32'bz (32-bit high-impedance), indicating that
the data on the read ports is undefined during a write operation.
b. Read Operation (When RW_En is 0):
- When RW_En is low (indicating a read operation), the code retrieves data from the register file
at the addresses specified by ReadAdress1 and ReadAdress2. The values are assigned to
ReadData1 and ReadData2, respectively.

5. End of always Block:

This marks the end of the always block

In summary, this Verilog module implements a 32-bit register file with two read ports and one write
port. It can be used in digital circuits to store and retrieve data, and it operates based on the clock signal
and the control signal RW_En.

2.2 RTL_Viewer
Explain:

Picture 1:

- The two Flip-Flops on both sides are Read/Wirite signals

- The Regis block is the block that stores the value of Writedata into the WriteAdress register
- Two ReadData blocks are connected to Regis as Data Out
Picture 2:

- Tri State ports are used to block the value of Data Out. When writing RW_En = 1, the values
cannot be read to ReadData and vice versa when RW_En = 0, the values are read to ReadData.

2.3 Waveform

Explain: With the first 5 clock cycles, we turn on RW_En (Write Signal) then write WriteAddres value as (0
-> 5) respectively and write the WriteData as (20 -> 25) respectively. After writing the values, we set
RW_En = 0 (Read Signal) to read the values just written to the register and we see that the values are
written as expected.