Functional Coverage of Up/Down Counter

Counter =>
Counter is a sequential logic circuit that generates a count in response to clock pulses, commonly used
for tasks like frequency division, timing or addressing in digital systems.
Up/Down Counter =>
An up/down counter is a versatile digital logic circuit that can increment or decrement its
count based on control signals, providing bi-directional counting in digital systems.

Functional Coverage in System Verilog

Functional coverage is user-defined coverage, in contrast with code coverage, which is automatically inferred from
the source. At the most abstract level, functional coverage specifies some values to observe at certain times in a
design or test bench, and counts how many times those values occur.
System Verilog implements functional coverage with cover-groups and cover directives. Because cover directives
are usually temporal and can inspect multiple signals and states in the same evaluation, they are usually inserted
by designers in the design source as “white box” testing – i.e., they specify and validate the expected behaviour
of a design. This allows the verification tool to observe when particular events occurs or assumption are violated.

bins =>
bins keep track/record of number of times user hits specific value of coverpoint expression.
Types of bins =>
i] Automatic/ Implicit bins =>
If user do not specify bins explicitly, simulator automatically creates bins for user
depending on the possible values of cover-point and auto_bin_max.
By default auto_bin_max value is 64.
ii] Explicit bins =>
Explicit bins are user defined bins in which coverage calculated only for the specified bins.
With explicit bins we could create own bins and then depends number of bins we have calculated coverage.

Covergroup =>
Covergroup is something that will encapsulate all coverpoint or coverage point that user stressing.
Coverpoint =>
Coverpoint could variable that have multiple bins depending on the specific values user is targeting.
Cross coverage =>
Cross coverage allows having a cross product (i.e., cartesian product) between two or more
variables or coverage points within the same covergroup.
OR
Cross coverage is nothing but a set of cross products of variables or coverage points.
 Counter Input Output Signals

clk: Clock input signal which is used to synchronize and control the operation of the counter.
rst: Reset input signal which resets the counter to its initial state.
up: Up/down control input signal. When it will high the counter counts up otherwise counts down.
load: Load control input signal. When activated, it loads a new value into the counter based on the “loadin” signal.
loadin: 8 - bit input data bus. When the load signal is active, the value present on this bus is loaded into the counter.
y: 8 - bit output data bus. It represents the current value of the counter. The value on this bus can be read externally.

GitHub Code Repo: https://github.com/asimkhan8107/Counter-FC

Eda Play ground: https://edaplayground.com/x/Du4K

IDE: Eda playground

Simulator – Aldec Riviera Pro

Simulation Result=>

Coverage Report =>

Check my previous posts : “RTL Design of AXI Stream Protocol”.
“RTL Design of UART Protocol”.